diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:22 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:22 -0600 |
commit | cdacbe734a9e6e0f20e0a37ef694995373b83f66 (patch) | |
tree | 775ea93dcd7acd5255818739ac78523634c8cc62 /src/cpu/inorder/inorder_dyn_inst.cc | |
parent | f4f5d03ed211571f07f13ea9d5df0d70f3101aa3 (diff) | |
download | gem5-cdacbe734a9e6e0f20e0a37ef694995373b83f66.tar.xz |
ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
This change modifies the way prefetches work. They are now like normal loads
that don't writeback a register. Previously prefetches were supposed to call
prefetch() on the exection context, so they executed with execute() methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs
are blank, meaning that they get executed, but don't actually do anything.
On Alpha dead cache copy code was removed and prefetches are now normal ops.
They count as executed operations, but still don't do anything and IsMemRef is
not longer set on them.
On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch
instructions. The timing simple CPU doesn't try to do anything special for
prefetches now and they execute with the normal memory code path.
Diffstat (limited to 'src/cpu/inorder/inorder_dyn_inst.cc')
-rw-r--r-- | src/cpu/inorder/inorder_dyn_inst.cc | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index f672082f3..d848226c4 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -346,38 +346,6 @@ InOrderDynInst::syscall(int64_t callnum) #endif void -InOrderDynInst::prefetch(Addr addr, unsigned flags) -{ - cpu->prefetch(this); -} - -void -InOrderDynInst::writeHint(Addr addr, int size, unsigned flags) -{ - cpu->writeHint(this); -} - -/** - * @todo Need to find a way to get the cache block size here. - */ -Fault -InOrderDynInst::copySrcTranslate(Addr src) -{ - // Not currently supported. - return NoFault; -} - -/** - * @todo Need to find a way to get the cache block size here. - */ -Fault -InOrderDynInst::copy(Addr dest) -{ - // Not currently supported. - return NoFault; -} - -void InOrderDynInst::releaseReq(ResourceRequest* req) { std::list<ResourceRequest*>::iterator list_it = reqList.begin(); |