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author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:15 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:15 -0400 |
commit | 6211fe5d2ee00dae9cd72d9cccdc900241a8f9a2 (patch) | |
tree | ee0ac43983c31c9c22b7ea28e69725d033287ef4 /src/cpu/inorder/inorder_dyn_inst.cc | |
parent | 3603dd25efb70ec400e8ea1e76137e8e288e533a (diff) | |
download | gem5-6211fe5d2ee00dae9cd72d9cccdc900241a8f9a2.tar.xz |
inorder-float: Fix storage of FP results
inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access
because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from
the actual floating point register file, the model can figure out what it needs to store
Diffstat (limited to 'src/cpu/inorder/inorder_dyn_inst.cc')
-rw-r--r-- | src/cpu/inorder/inorder_dyn_inst.cc | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index 280740116..9609db22f 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -520,6 +520,7 @@ InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, } instResult[idx].tick = curTick; + instResult[idx].width = width; } /** Sets a FP register as a integer. */ @@ -527,13 +528,10 @@ void InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val, int width) { - if (width == 32) - instResult[idx].type = Float; - else if (width == 64) - instResult[idx].type = Double; - + instResult[idx].type = Integer; instResult[idx].val.integer = val; instResult[idx].tick = curTick; + instResult[idx].width = width; } /** Sets a misc. register. */ |