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author | Gabe Black <gblack@eecs.umich.edu> | 2010-08-13 06:16:02 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-08-13 06:16:02 -0700 |
commit | aa8c6e9c959eab4d516bc07593bea20ade9ad80c (patch) | |
tree | 3e0112e567da5dc1aa019f85458fbd9e37ad0cf2 /src/cpu/inorder/inorder_dyn_inst.cc | |
parent | 65dbcc6ea170e05ca2370a9a265a61668250fa98 (diff) | |
download | gem5-aa8c6e9c959eab4d516bc07593bea20ade9ad80c.tar.xz |
CPU: Add readBytes and writeBytes functions to the exec contexts.
Diffstat (limited to 'src/cpu/inorder/inorder_dyn_inst.cc')
-rw-r--r-- | src/cpu/inorder/inorder_dyn_inst.cc | 35 |
1 files changed, 27 insertions, 8 deletions
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index 13ec7a3ff..5486dedee 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -610,6 +610,13 @@ InOrderDynInst::deallocateContext(int thread_num) this->cpu->deallocateContext(thread_num); } +Fault +InOrderDynInst::readBytes(Addr addr, uint8_t *data, + unsigned size, unsigned flags) +{ + return cpu->read(this, addr, data, size, flags); +} + template<class T> inline Fault InOrderDynInst::read(Addr addr, T &data, unsigned flags) @@ -618,8 +625,11 @@ InOrderDynInst::read(Addr addr, T &data, unsigned flags) traceData->setAddr(addr); traceData->setData(data); } - - return cpu->read(this, addr, data, flags); + Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags); + data = TheISA::gtoh(data); + if (traceData) + traceData->setData(data); + return fault; } #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -663,20 +673,29 @@ InOrderDynInst::read(Addr addr, int32_t &data, unsigned flags) return read(addr, (uint32_t&)data, flags); } +Fault +InOrderDynInst::writeBytes(uint8_t *data, unsigned size, + Addr addr, unsigned flags, uint64_t *res) +{ + assert(sizeof(storeData) >= size); + memcpy(&storeData, data, size); + return cpu->write(this, (uint8_t *)&storeData, size, addr, flags, res); +} + template<class T> inline Fault InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res) { - if (traceData) { - traceData->setAddr(addr); - traceData->setData(data); - } - storeData = data; DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting store data to %#x.\n", threadNumber, seqNum, storeData); - return cpu->write(this, data, addr, flags, res); + if (traceData) { + traceData->setAddr(addr); + traceData->setData(data); + } + storeData = TheISA::htog(data); + return writeBytes((uint8_t*)&data, sizeof(T), addr, flags, res); } #ifndef DOXYGEN_SHOULD_SKIP_THIS |