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authorKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:41 -0400
committerKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:41 -0400
commit2dae0e87358e693f120c2da925801944a4727a91 (patch)
treeb2f70ef7b5fa9e763ba49e0c475fad15af7b0d78 /src/cpu/inorder/inorder_dyn_inst.hh
parent8c0def8d0347e9a7b84f21895c5cbd94eba9a09a (diff)
downloadgem5-2dae0e87358e693f120c2da925801944a4727a91.tar.xz
inorder: use separate float-reg bits function in dyninst
this will make sure we get the correct view of a FP register
Diffstat (limited to 'src/cpu/inorder/inorder_dyn_inst.hh')
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.hh10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 54c2e16c5..b655de380 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -213,6 +213,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
None,
Integer,
Float,
+ FloatBits,
Double
};
@@ -889,7 +890,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
return instResult[idx].type;
}
- uint64_t readIntResult(int idx)
+ IntReg readIntResult(int idx)
{
return instResult[idx].res.intVal;
}
@@ -899,9 +900,14 @@ class InOrderDynInst : public FastAlloc, public RefCounted
return instResult[idx].res.fpVal.f;
}
+ FloatRegBits readFloatBitsResult(int idx)
+ {
+ return instResult[idx].res.fpVal.i;
+ }
+
Tick readResultTime(int idx) { return instResult[idx].tick; }
- uint64_t* getIntResultPtr(int idx) { return &instResult[idx].res.intVal; }
+ IntReg* getIntResultPtr(int idx) { return &instResult[idx].res.intVal; }
/** This is the interface that an instruction will use to write
* it's destination register.