inorder: dyn inst initialization

remove constructors that werent being used (it just gets confusing)
use initialization list for all the variables instead of relying on initVars()
function

1 files changed, 13 insertions, 35 deletions

diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 0e6be3da2..04f9abb96 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -107,17 +107,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
 
   public:
     /** BaseDynInst constructor given a binary instruction.
-     *  @param inst The binary instruction.
-     *  @param PC The PC of the instruction.
-     *  @param predPC The predicted next PC.
-     *  @param seq_num The sequence number of the instruction.
-     *  @param cpu Pointer to the instruction's CPU.
-     */
-    InOrderDynInst(ExtMachInst inst, const TheISA::PCState &PC,
-                   const TheISA::PCState &predPC, InstSeqNum seq_num,
-                   InOrderCPU *cpu);
-
-    /** BaseDynInst constructor given a binary instruction.
      *  @param seq_num The sequence number of the instruction.
      *  @param cpu Pointer to the instruction's CPU.
      *  NOTE: Must set Binary Instrution through Member Function
@@ -125,14 +114,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
                    InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
 
-    /** BaseDynInst constructor given a StaticInst pointer.
-     *  @param _staticInst The StaticInst for this BaseDynInst.
-     */
-    InOrderDynInst(StaticInstPtr &_staticInst);
-
-    /** Skeleton Constructor. */
-    InOrderDynInst();
-
     /** InOrderDynInst destructor. */
     ~InOrderDynInst();
 
@@ -219,12 +200,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     /** The effective physical address. */
     Addr physEffAddr;
 
-    /** Effective virtual address for a copy source. */
-    Addr copySrcEffAddr;
-
-    /** Effective physical address for a copy source. */
-    Addr copySrcPhysEffAddr;
-
     /** The memory request flags (from translation). */
     unsigned memReqFlags;
 
@@ -253,8 +228,11 @@ class InOrderDynInst : public FastAlloc, public RefCounted
         Tick tick;
 
         InstResult()
-            : type(None), tick(0)
-        {}
+          : type(None), tick(0)
+        {
+          val.integer = 0;
+          val.dbl = 0;
+        }
     };
 
     /** The source of the instruction; assumes for now that there's only one
@@ -273,10 +251,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     /** Predicted next PC. */
     TheISA::PCState predPC;
 
-    /** Address to fetch from */
-    Addr fetchAddr;
-
     /** Address to get/write data from/to */
+    /* Fetching address when inst. starts, Data address for load/store after fetch*/
     Addr memAddr;
 
     /** Whether or not the source register is ready.
@@ -477,7 +453,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted
         curSkedEntry++;
 
         if (inFrontEnd && curSkedEntry == frontSked_end) {
-            assert(backSked != NULL);
+          DPRINTF(InOrderDynInst, "[sn:%i] Switching to "
+                  "back end schedule.\n", seqNum);
+          assert(backSked != NULL);
             curSkedEntry.init(backSked);
             curSkedEntry = backSked->begin();
             inFrontEnd = false;
@@ -485,6 +463,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted
             return true;
         }
 
+        DPRINTF(InOrderDynInst, "[sn:%i] Next Stage: %i "
+                "Next Resource: %i.\n", seqNum, curSkedEntry->stageNum,
+                curSkedEntry->resNum);
+
         return false;
     }
 
@@ -997,10 +979,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     bool eaCalcDone;
 
   public:
-    /** Whether or not the memory operation is done. */
-    bool memOpDone;
-
-  public:
     /** Load queue index. */
     int16_t lqIdx;