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authorKorey Sewell <ksewell@umich.edu>2010-01-31 18:27:58 -0500
committerKorey Sewell <ksewell@umich.edu>2010-01-31 18:27:58 -0500
commit069b38c0d546708491d0da84668ba32f82ca7cb8 (patch)
tree75e31122a4b77bddb6f3c5f0f35251c134046cba /src/cpu/inorder/pipeline_stage.cc
parentaacc5cb205c17a91545a5d8209f5c4bda85543a9 (diff)
downloadgem5-069b38c0d546708491d0da84668ba32f82ca7cb8.tar.xz
inorder: track last branch committed
when threads are switching in/out the CPU, we need to keep track of special cases like branches. Add appropriate variables in ThreadState t track this and then use these variables when updating pc after context switch
Diffstat (limited to 'src/cpu/inorder/pipeline_stage.cc')
-rw-r--r--src/cpu/inorder/pipeline_stage.cc9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index 620951e34..55ee3ad12 100644
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -568,15 +568,18 @@ PipelineStage::activateThread(ThreadID tid)
} else {
DynInstPtr inst = switchedOutBuffer[tid];
- DPRINTF(InOrderStage,"[tid:%i]: Re-Inserting [sn:%lli] PC:%#x into stage skidBuffer %i\n",
- tid, inst->seqNum, inst->readPC(), inst->threadNumber);
+ DPRINTF(InOrderStage,"[tid:%i]: Re-Inserting [sn:%lli] PC:%#x into "
+ "stage skidBuffer %i\n", tid, inst->seqNum,
+ inst->readPC(), inst->threadNumber);
// Make instruction available for pipeline processing
skidBuffer[tid].push(inst);
// Update PC so that we start fetching after this instruction to prevent
// "double"-execution of instructions
- cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)ResourcePool::UpdateAfterContextSwitch, inst, 0, 0, tid);
+ cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)
+ ResourcePool::UpdateAfterContextSwitch,
+ inst, 0, 0, tid);
// Clear switchout buffer
switchedOutBuffer[tid] = NULL;