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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:40 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:40 -0400 |
| commit | 561c33f0824a705cb360ecb4ae3bf8cfd490f007 (patch) | |
| tree | 7fb92ebc9a8f09ceacb8ad8e60e60990a9939621 /src/cpu/inorder/pipeline_stage.cc | |
| parent | c4deabfb97928f81acb0d66338426cb5f2687c37 (diff) | |
| download | gem5-561c33f0824a705cb360ecb4ae3bf8cfd490f007.tar.xz | |
inorder: dont handle multiple faults on same cycle
if a faulting instruction reaches an execution unit,
then ignore it and pass it through the pipeline.
Once we recognize the fault in the graduation unit,
dont allow a second fault to creep in on the same cycle.
Diffstat (limited to 'src/cpu/inorder/pipeline_stage.cc')
| -rw-r--r-- | src/cpu/inorder/pipeline_stage.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc index 3c945d31c..ac180d3c0 100644 --- a/src/cpu/inorder/pipeline_stage.cc +++ b/src/cpu/inorder/pipeline_stage.cc @@ -130,6 +130,7 @@ PipelineStage::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) timeBuffer = tb_ptr; // Setup wire to write information back to fetch. + // @todo: should this be writing to the next stage => -1 and reading from is (0)??? toPrevStages = timeBuffer->getWire(0); // Create wires to get information from proper places in time buffer. |