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authorKorey Sewell <ksewell@umich.edu>2010-01-31 18:27:49 -0500
committerKorey Sewell <ksewell@umich.edu>2010-01-31 18:27:49 -0500
commitaacc5cb205c17a91545a5d8209f5c4bda85543a9 (patch)
tree4d13dcfbb71ceba02f2559e8a4b366228599df95 /src/cpu/inorder/pipeline_stage.cc
parent90d3b45a566847fe15095b92238e32973ad9cc0e (diff)
downloadgem5-aacc5cb205c17a91545a5d8209f5c4bda85543a9.tar.xz
inorder: add updatePC event to resPool
this will be used for when a thread comes back from a cache miss, it needs to update the PCs because the inst might of been a branch or delayslot in which the next PC isnt always a straight addition
Diffstat (limited to 'src/cpu/inorder/pipeline_stage.cc')
-rw-r--r--src/cpu/inorder/pipeline_stage.cc7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index ef91f206b..620951e34 100644
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -571,10 +571,15 @@ PipelineStage::activateThread(ThreadID tid)
DPRINTF(InOrderStage,"[tid:%i]: Re-Inserting [sn:%lli] PC:%#x into stage skidBuffer %i\n",
tid, inst->seqNum, inst->readPC(), inst->threadNumber);
+ // Make instruction available for pipeline processing
skidBuffer[tid].push(inst);
- switchedOutBuffer[tid] = NULL;
+ // Update PC so that we start fetching after this instruction to prevent
+ // "double"-execution of instructions
+ cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)ResourcePool::UpdateAfterContextSwitch, inst, 0, 0, tid);
+ // Clear switchout buffer
+ switchedOutBuffer[tid] = NULL;
switchedOutValid[tid] = false;
}
}