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| author | Korey Sewell <ksewell@umich.edu> | 2011-02-18 14:28:30 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-02-18 14:28:30 -0500 |
| commit | d64226750ef9b2ac85c116f90cdfdb2a755b32d4 (patch) | |
| tree | f9e0e41a6008fdf3fa67a8f014dab9b54ffd37e5 /src/cpu/inorder/pipeline_stage.cc | |
| parent | c8837290251a300114975861575f59a58990b51a (diff) | |
| download | gem5-d64226750ef9b2ac85c116f90cdfdb2a755b32d4.tar.xz | |
inorder: remove request map, use request vector
take away all instances of reqMap in the code and make all references use the built-in
request vectors inside of each resource. The request map was dynamically allocating
a request per instruction. The request vector just allocates N number of requests
during instantiation and then the surrounding code is fixed up to reuse those N requests
***
setRequest() and clearRequest() are the new accessors needed to define a new
request in a resource
Diffstat (limited to 'src/cpu/inorder/pipeline_stage.cc')
| -rw-r--r-- | src/cpu/inorder/pipeline_stage.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc index 5de963b0e..610b6f264 100644 --- a/src/cpu/inorder/pipeline_stage.cc +++ b/src/cpu/inorder/pipeline_stage.cc @@ -938,6 +938,7 @@ PipelineStage::processInstSchedule(DynInstPtr inst,int &reqs_processed) "\n", tid, inst->seqNum, cpu->resPool->name(res_num)); ResReqPtr req = cpu->resPool->request(res_num, inst); + assert(req->valid); if (req->isCompleted()) { DPRINTF(InOrderStage, "[tid:%i]: [sn:%i] request to %s " |