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| author | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:28:59 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:28:59 -0500 |
| commit | 0b29c2d057d2d6f4f8b9b7853da91bcb283e805c (patch) | |
| tree | e594abc10fc92baaed872fe7139153bd5a86ffcf /src/cpu/inorder/pipeline_stage.cc | |
| parent | ffa9ecb1fa71f1fe89a65975b2c558e312bbfbc8 (diff) | |
| download | gem5-0b29c2d057d2d6f4f8b9b7853da91bcb283e805c.tar.xz | |
inorder: ctxt switch stats
- m5 line enforcement on use_def.cc,hh
Diffstat (limited to 'src/cpu/inorder/pipeline_stage.cc')
| -rw-r--r-- | src/cpu/inorder/pipeline_stage.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc index e601edfcc..550952947 100644 --- a/src/cpu/inorder/pipeline_stage.cc +++ b/src/cpu/inorder/pipeline_stage.cc @@ -570,6 +570,9 @@ PipelineStage::activateThread(ThreadID tid) // Clear switchout buffer switchedOutBuffer[tid] = NULL; switchedOutValid[tid] = false; + + // Update any CPU stats based off context switches + cpu->updateContextSwitchStats(); } } |