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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:41 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:41 -0400 |
| commit | 716e447da8424386f2c3448c17891927aeb49f67 (patch) | |
| tree | 7cd5ba23161faa0a5337b5a7add3f75569bbfd76 /src/cpu/inorder/pipeline_stage.cc | |
| parent | 83a0fd24f72ed46e71c015c23b723c04d39ca93c (diff) | |
| download | gem5-716e447da8424386f2c3448c17891927aeb49f67.tar.xz | |
inorder: handle serializing instructions
including IPR accesses and store-conditionals. These class of instructions will not
execute correctly in a superscalar machine
Diffstat (limited to 'src/cpu/inorder/pipeline_stage.cc')
| -rw-r--r-- | src/cpu/inorder/pipeline_stage.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc index ac180d3c0..4dec38629 100644 --- a/src/cpu/inorder/pipeline_stage.cc +++ b/src/cpu/inorder/pipeline_stage.cc @@ -1093,6 +1093,7 @@ PipelineStage::sendInstToNextStage(DynInstPtr inst) // Take note of trace data for this inst & stage if (inst->traceData) { + //@todo: exec traces are broke. fix them inst->traceData->setStageCycle(stageNum, curTick()); } |