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author | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:26:32 -0500 |
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committer | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:26:32 -0500 |
commit | e1fcc6498017574735362636791f9ad73fb39b04 (patch) | |
tree | da58049ba1b2c6b52dced5aa8928cb6fc27485ab /src/cpu/inorder/pipeline_stage.cc | |
parent | 4a945aab1958d39fcfea4608715e77d5112809cf (diff) | |
download | gem5-e1fcc6498017574735362636791f9ad73fb39b04.tar.xz |
inorder: activate thread on cache miss
-Support ability to activate next ready thread after a cache miss
through the activateNextReadyContext/Thread() functions
-To support this a "readyList" of thread ids is added
-After a cache miss, thread will suspend and then call
activitynextreadythread
Diffstat (limited to 'src/cpu/inorder/pipeline_stage.cc')
-rw-r--r-- | src/cpu/inorder/pipeline_stage.cc | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc index 1fd7150da..30a3733b0 100644 --- a/src/cpu/inorder/pipeline_stage.cc +++ b/src/cpu/inorder/pipeline_stage.cc @@ -951,7 +951,15 @@ PipelineStage::processInstSchedule(DynInstPtr inst) // Remove Thread From Pipeline & Resource Pool inst->squashingStage = stageNum; inst->bdelaySeqNum = inst->seqNum; - cpu->squashFromMemStall(inst, tid); + cpu->squashFromMemStall(inst, tid); + + // Switch On Cache Miss + //===================== + // Suspend Thread at end of cycle + cpu->suspendContext(tid); + + // Activate Next Ready Thread at end of cycle + cpu->activateNextReadyContext(); } break; |