diff options
author | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:28:31 -0500 |
---|---|---|
committer | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:28:31 -0500 |
commit | 4d749472e3cb97ff0421fbf5cbc53d9c89ecfa45 (patch) | |
tree | 003805dffa52427f140e92b2d0e9163c1f12398c /src/cpu/inorder/pipeline_stage.hh | |
parent | b4e0ef78379dd5bab0ee6ec824bca3f51dd484c6 (diff) | |
download | gem5-4d749472e3cb97ff0421fbf5cbc53d9c89ecfa45.tar.xz |
inorder: enforce stage bandwidth
each stage keeps track of insts_processed on a per_thread basis but we should
be keeping that on a total basis inorder to enforce stage width limits
Diffstat (limited to 'src/cpu/inorder/pipeline_stage.hh')
-rw-r--r-- | src/cpu/inorder/pipeline_stage.hh | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/cpu/inorder/pipeline_stage.hh b/src/cpu/inorder/pipeline_stage.hh index dfe1ac7c3..920734e6a 100644 --- a/src/cpu/inorder/pipeline_stage.hh +++ b/src/cpu/inorder/pipeline_stage.hh @@ -178,7 +178,7 @@ class PipelineStage virtual void processInsts(ThreadID tid); /** Process all resources on an instruction's resource schedule */ - virtual bool processInstSchedule(DynInstPtr inst); + virtual bool processInstSchedule(DynInstPtr inst, int &reqs_processed); /** Is there room in the next stage buffer for this instruction? */ virtual bool canSendInstToStage(unsigned stage_num); @@ -270,6 +270,11 @@ class PipelineStage std::vector<DynInstPtr> switchedOutBuffer; std::vector<bool> switchedOutValid; + /** Instructions that we've processed this tick + * NOTE: "Processed" means completed at least 1 instruction request + */ + unsigned instsProcessed; + /** Queue of all instructions coming from previous stage on this cycle. */ std::queue<DynInstPtr> insts[ThePipeline::MaxThreads]; |