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| author | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:08:16 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:08:16 -0500 |
| commit | be17617990ea2b95e0f08324570b2bbf93dee1f0 (patch) | |
| tree | cdfe04692ce59363c46a7aec13827f85a0366e0d /src/cpu/inorder/pipeline_stage.hh | |
| parent | 050944dd7388231a334b81adf65e535058cf13fb (diff) | |
| download | gem5-be17617990ea2b95e0f08324570b2bbf93dee1f0.tar.xz | |
inorder: pipe. stage inst. buffering
use skidbuffer as only location for instructions between stages. before,
we had the insts queue from the prior stage and the skidbuffer for the
current stage, but that gets confusing and this consolidation helps
when handling squash cases
Diffstat (limited to 'src/cpu/inorder/pipeline_stage.hh')
| -rw-r--r-- | src/cpu/inorder/pipeline_stage.hh | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/cpu/inorder/pipeline_stage.hh b/src/cpu/inorder/pipeline_stage.hh index fb8ec593e..dfa88de87 100644 --- a/src/cpu/inorder/pipeline_stage.hh +++ b/src/cpu/inorder/pipeline_stage.hh @@ -184,11 +184,6 @@ class PipelineStage /** Send an instruction to the next stage buffer */ bool sendInstToNextStage(DynInstPtr inst); - /** Inserts a thread's instructions into the skid buffer, to be staged - * once stage unblocks. - */ - virtual void skidInsert(ThreadID tid); - /** Total size of all skid buffers */ int skidSize(); |