diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2015-04-20 12:46:35 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-04-20 12:46:35 -0400 |
commit | cd76e34056afab83697beef1d1ced94ee671a20d (patch) | |
tree | 8adaa80ba72593bdf67103ad5cd0a072b95e8acb /src/cpu/inorder/pipeline_traits.5stage.hh | |
parent | 076ea249ae47b935bea424954174f33fdecb7fcc (diff) | |
download | gem5-cd76e34056afab83697beef1d1ced94ee671a20d.tar.xz |
cpu: Remove the InOrderCPU from the tree
This patch takes the final step in removing the InOrderCPU from the
tree. Rest in peace.
The MinorCPU is now used to model an in-order microarchitecture, and
long term the MinorCPU will eventually be renamed InOrderCPU.
Diffstat (limited to 'src/cpu/inorder/pipeline_traits.5stage.hh')
-rw-r--r-- | src/cpu/inorder/pipeline_traits.5stage.hh | 145 |
1 files changed, 0 insertions, 145 deletions
diff --git a/src/cpu/inorder/pipeline_traits.5stage.hh b/src/cpu/inorder/pipeline_traits.5stage.hh deleted file mode 100644 index 5f1587587..000000000 --- a/src/cpu/inorder/pipeline_traits.5stage.hh +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - * - */ - -#ifndef __CPU_INORDER_PIPELINE_IMPL_HH__ -#define __CPU_INORDER_PIPELINE_IMPL_HH__ - -#include <list> -#include <queue> -#include <vector> - -#include "arch/isa_traits.hh" - -class InOrderDynInst; - -/* This Namespace contains constants, typedefs, functions and - * objects specific to the Pipeline Implementation. - */ -namespace ThePipeline { - // Pipeline Constants - const unsigned NumStages = 5; - const unsigned MaxThreads = 3; - const unsigned StageWidth = 1; - const unsigned BackEndStartStage = 2; - - // Enumerated List of Resources The Pipeline Uses - enum ResourceList { - FetchSeq = 0, - ITLB, - ICache, - Decode, - BPred, - FetchBuff, - RegManager, - AGEN, - ExecUnit, - DTLB, - DCache, - Grad, - FetchBuff2 - }; - - // Expand this as necessary for your inter stage buffer sizes - static const unsigned interStageBuffSize[] = { - StageWidth, /* Stage 0 - 1 */ - StageWidth, /* Stage 1 - 2 */ - StageWidth, /* Stage 2 - 3 */ - StageWidth, /* Stage 3 - 4 */ - StageWidth, /* Stage 4 - 5 */ - StageWidth, /* Stage 5 - 6 */ - StageWidth, /* Stage 6 - 7 */ - StageWidth, /* Stage 7 - 8 */ - StageWidth /* Stage 8 - 9 */ - }; - - typedef InOrderCPUParams Params; - typedef RefCountingPtr<InOrderDynInst> DynInstPtr; - - ////////////////////////// - // RESOURCE SCHEDULING - ////////////////////////// - struct ScheduleEntry { - ScheduleEntry(int stage_num, int _priority, int res_num, int _cmd = 0, - int _idx = 0) : - stageNum(stage_num), resNum(res_num), cmd(_cmd), - idx(_idx), priority(_priority) - { } - virtual ~ScheduleEntry(){} - - // Stage number to perform this service. - int stageNum; - - // Resource ID to access - int resNum; - - // See specific resource for meaning - unsigned cmd; - - // See specific resource for meaning - unsigned idx; - - // Some Resources May Need Priority? - int priority; - }; - - struct entryCompare { - bool operator()(const ScheduleEntry* lhs, const ScheduleEntry* rhs) const - { - // Prioritize first by stage number that the resource is needed - if (lhs->stageNum > rhs->stageNum) { - return true; - } else if (lhs->stageNum == rhs->stageNum) { - /*if (lhs->resNum > rhs->resNum) { - return true; - } else { - return false; - }*/ - - if (lhs->priority > rhs->priority) { - return true; - } else { - return false; - } - } else { - return false; - } - } - }; - - - typedef std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>, - entryCompare> ResSchedule; - - void createFrontEndSchedule(DynInstPtr &inst); - bool createBackEndSchedule(DynInstPtr &inst); - int getNextPriority(DynInstPtr &inst, int stage_num); -}; -#endif |