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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
| commit | 5127ea226a0a2cd75334c5af4cb182a1fd9b6cf1 (patch) | |
| tree | 7ca2a867dd44c4c4b2e4d7de44ff04ec4cfd88c0 /src/cpu/inorder/pipeline_traits.cc | |
| parent | 98b1452058ae7e82df7cb7c0373c62a97981a2b9 (diff) | |
| download | gem5-5127ea226a0a2cd75334c5af4cb182a1fd9b6cf1.tar.xz | |
inorder-unified-tlb: use unified TLB instead of old TLB model
Diffstat (limited to 'src/cpu/inorder/pipeline_traits.cc')
| -rw-r--r-- | src/cpu/inorder/pipeline_traits.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/inorder/pipeline_traits.cc b/src/cpu/inorder/pipeline_traits.cc index 1c17b0d3f..150115138 100644 --- a/src/cpu/inorder/pipeline_traits.cc +++ b/src/cpu/inorder/pipeline_traits.cc @@ -101,7 +101,7 @@ bool createBackEndSchedule(DynInstPtr &inst) } else if ( inst->isMemRef() ) { if ( inst->isLoad() ) { E->needs(AGEN, AGENUnit::GenerateAddr); - E->needs(DTLB, TLBUnit::DataLookup); + E->needs(DTLB, TLBUnit::DataReadLookup); E->needs(DCache, CacheUnit::InitiateReadData); } } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) { @@ -122,7 +122,7 @@ bool createBackEndSchedule(DynInstPtr &inst) } else if ( inst->isStore() ) { M->needs(RegManager, UseDefUnit::ReadSrcReg, 1); M->needs(AGEN, AGENUnit::GenerateAddr); - M->needs(DTLB, TLBUnit::DataLookup); + M->needs(DTLB, TLBUnit::DataWriteLookup); M->needs(DCache, CacheUnit::InitiateWriteData); } |