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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
| commit | 2012202b06a620998709f605f8f8692ad718294d (patch) | |
| tree | 43a4817c6889723d480e7c66c0b22cfe022cb0ea /src/cpu/inorder/pipeline_traits.cc | |
| parent | b569f8f0ed8dcf32347f0d4f68d2d7572a5d1353 (diff) | |
| download | gem5-2012202b06a620998709f605f8f8692ad718294d.tar.xz | |
inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
* * *
Diffstat (limited to 'src/cpu/inorder/pipeline_traits.cc')
| -rw-r--r-- | src/cpu/inorder/pipeline_traits.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/inorder/pipeline_traits.cc b/src/cpu/inorder/pipeline_traits.cc index eb899452a..1c17b0d3f 100644 --- a/src/cpu/inorder/pipeline_traits.cc +++ b/src/cpu/inorder/pipeline_traits.cc @@ -99,8 +99,8 @@ bool createBackEndSchedule(DynInstPtr &inst) if ( inst->isNonSpeculative() ) { // skip execution of non speculative insts until later } else if ( inst->isMemRef() ) { - E->needs(AGEN, AGENUnit::GenerateAddr); if ( inst->isLoad() ) { + E->needs(AGEN, AGENUnit::GenerateAddr); E->needs(DTLB, TLBUnit::DataLookup); E->needs(DCache, CacheUnit::InitiateReadData); } @@ -121,6 +121,7 @@ bool createBackEndSchedule(DynInstPtr &inst) M->needs(DCache, CacheUnit::CompleteReadData); } else if ( inst->isStore() ) { M->needs(RegManager, UseDefUnit::ReadSrcReg, 1); + M->needs(AGEN, AGENUnit::GenerateAddr); M->needs(DTLB, TLBUnit::DataLookup); M->needs(DCache, CacheUnit::InitiateWriteData); } |