diff options
| author | Korey Sewell <ksewell@umich.edu> | 2011-02-12 10:14:36 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-02-12 10:14:36 -0500 |
| commit | 6713dbfe080df4dd04b0f29b5f2fbd6e221ffebf (patch) | |
| tree | 9bc390854c24cf308f93fe7ab44928a8facaff59 /src/cpu/inorder/pipeline_traits.hh | |
| parent | af67631790afbfeba01b05f7ae2ca54ae27428f1 (diff) | |
| download | gem5-6713dbfe080df4dd04b0f29b5f2fbd6e221ffebf.tar.xz | |
inorder: cache instruction schedules
first step in a optimization to not dynamically allocate an instruction schedule
for every instruction but rather used cached schedules
Diffstat (limited to 'src/cpu/inorder/pipeline_traits.hh')
| -rw-r--r-- | src/cpu/inorder/pipeline_traits.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/inorder/pipeline_traits.hh b/src/cpu/inorder/pipeline_traits.hh index df964e254..2c4e44339 100644 --- a/src/cpu/inorder/pipeline_traits.hh +++ b/src/cpu/inorder/pipeline_traits.hh @@ -77,6 +77,7 @@ namespace ThePipeline { // RESOURCE SCHEDULING ////////////////////////// typedef ResourceSked ResSchedule; + typedef ResourceSked* RSkedPtr; void createFrontEndSchedule(DynInstPtr &inst); bool createBackEndSchedule(DynInstPtr &inst); |