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| author | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:25:27 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:25:27 -0500 |
| commit | a892af7b261e1c48b06ccbded5551e958c778414 (patch) | |
| tree | 62f582c53677bb485f791b97ad1ed98ca90c2a10 /src/cpu/inorder/pipeline_traits.hh | |
| parent | 0e96798fe0a56936f8590dbd301f2b07a1850e22 (diff) | |
| download | gem5-a892af7b261e1c48b06ccbded5551e958c778414.tar.xz | |
inorder: dont allow early loads
- loads were happening on same cycle as the address was generated which is slightly
unrealistic. Instead, force address generation to be on separate cycle from load
initiation
- also, mark the stages in a more traditional way (F-D-X-M-W)
Diffstat (limited to 'src/cpu/inorder/pipeline_traits.hh')
| -rw-r--r-- | src/cpu/inorder/pipeline_traits.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/inorder/pipeline_traits.hh b/src/cpu/inorder/pipeline_traits.hh index 3c28894e7..ddc8a3ad7 100644 --- a/src/cpu/inorder/pipeline_traits.hh +++ b/src/cpu/inorder/pipeline_traits.hh @@ -113,7 +113,8 @@ namespace ThePipeline { }; struct entryCompare { - bool operator()(const ScheduleEntry* lhs, const ScheduleEntry* rhs) const + bool operator()(const ScheduleEntry* lhs, const ScheduleEntry* rhs) + const { // Prioritize first by stage number that the resource is needed if (lhs->stageNum > rhs->stageNum) { |