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| author | Korey Sewell <ksewell@umich.edu> | 2009-03-04 13:17:07 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-03-04 13:17:07 -0500 |
| commit | f69b018571a6396d0e679d4d0eceb47ef4496530 (patch) | |
| tree | 00e8e6ad7b94e17a9ca328e37fb8bdbd5225cbf9 /src/cpu/inorder/pipeline_traits.hh | |
| parent | f98e9161a83cd9bafbe7e5612db344a8b5cb2ae1 (diff) | |
| download | gem5-f69b018571a6396d0e679d4d0eceb47ef4496530.tar.xz | |
make handling of interstage buffers (i.e. StageQueues) more consistent: (1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to get StageQueue size for all threads
Diffstat (limited to 'src/cpu/inorder/pipeline_traits.hh')
0 files changed, 0 insertions, 0 deletions