inorder-tlb-cunit: merge the TLB as implicit to any memory access

TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst
since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory
and the result is checked before it's sent out to memory.
* * *

1 files changed, 3 insertions, 4 deletions

diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh
index 0378c0f50..71270241f 100644
--- a/src/cpu/inorder/resource.hh
+++ b/src/cpu/inorder/resource.hh
@@ -140,15 +140,14 @@ class Resource {
      *  if instruction is actually in resource before
      *  trying to do access.Needs to be defined for derived units.
      */
-    virtual Fault doDataAccess(DynInstPtr inst, uint64_t *res=NULL)
-    { panic("doDataAccess undefined for %s", name()); return NoFault; }
+    virtual Fault doCacheAccess(DynInstPtr inst, uint64_t *res=NULL)
+    { panic("doCacheAccess undefined for %s", name()); return NoFault; }
 
     virtual void prefetch(DynInstPtr inst)
     { panic("prefetch undefined for %s", name()); }
 
     virtual void writeHint(DynInstPtr inst)
-    { panic("doDataAccess undefined for %s", name()); }
-
+    { panic("writeHint undefined for %s", name()); }
 
     /** Squash All Requests After This Seq Num */
     virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);