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author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:16 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:16 -0400 |
commit | db2b72138052ad96d808d8286bd2598c96f96a31 (patch) | |
tree | e2290ee7614146f869e7dde2d1978b47b10fc743 /src/cpu/inorder/resource_pool.cc | |
parent | 3a057bdbb10a265fb36f7827cd06142ad1624530 (diff) | |
download | gem5-db2b72138052ad96d808d8286bd2598c96f96a31.tar.xz |
inorder-tlb-cunit: merge the TLB as implicit to any memory access
TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst
since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory
and the result is checked before it's sent out to memory.
* * *
Diffstat (limited to 'src/cpu/inorder/resource_pool.cc')
-rw-r--r-- | src/cpu/inorder/resource_pool.cc | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/cpu/inorder/resource_pool.cc b/src/cpu/inorder/resource_pool.cc index 2187e2818..5cb55b89b 100644 --- a/src/cpu/inorder/resource_pool.cc +++ b/src/cpu/inorder/resource_pool.cc @@ -50,8 +50,6 @@ ResourcePool::ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params) // -------------------------------------------------- resources.push_back(new FetchSeqUnit("Fetch-Seq-Unit", FetchSeq, StageWidth * 2, 0, _cpu, params)); - resources.push_back(new TLBUnit("I-TLB", ITLB, StageWidth, 0, _cpu, params)); - memObjects.push_back(ICache); resources.push_back(new CacheUnit("icache_port", ICache, StageWidth * MaxThreads, 0, _cpu, params)); @@ -69,8 +67,6 @@ ResourcePool::ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params) resources.push_back(new MultDivUnit("Mult-Div-Unit", MDU, 5, 0, _cpu, params)); - resources.push_back(new TLBUnit("D-TLB", DTLB, StageWidth, 0, _cpu, params)); - memObjects.push_back(DCache); resources.push_back(new CacheUnit("dcache_port", DCache, StageWidth * MaxThreads, 0, _cpu, params)); @@ -205,7 +201,6 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst, inst->bdelaySeqNum, inst->readTid()); mainEventQueue.schedule(res_pool_event, curTick + cpu->ticks(delay)); - } break; @@ -256,7 +251,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst, break; default: - DPRINTF(Resource, "Ignoring Unrecognized CPU Event Type #%s.\n", InOrderCPU::eventNames[e_type]); + DPRINTF(Resource, "Ignoring Unrecognized CPU Event (%s).\n", InOrderCPU::eventNames[e_type]); ; // If Resource Pool doesnt recognize event, we ignore it. } } |