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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:36 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:36 -0400 |
| commit | 7dea79535c87b68b5fc6143190d09b8fc364f2aa (patch) | |
| tree | 3f30f0716de709f86b9adaa746f0b3e312203cef /src/cpu/inorder/resources/cache_unit.cc | |
| parent | 061b369d288ba4e3fdb145c025fb4d80378cb851 (diff) | |
| download | gem5-7dea79535c87b68b5fc6143190d09b8fc364f2aa.tar.xz | |
inorder: implement trap handling
Diffstat (limited to 'src/cpu/inorder/resources/cache_unit.cc')
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index c1a3590be..760fdb134 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -441,9 +441,10 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size, cache_req->tlbStall = true; + // schedule a time to process the tlb miss. + // latency hardcoded to 1 (for now), but will be updated + // when timing translation gets added in scheduleEvent(slot_idx, 1); - - cpu->trap(inst->fault, tid, inst); } else { DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated " "to phys. addr:%08p.\n", tid, inst->seqNum, @@ -1072,6 +1073,11 @@ CacheUnitEvent::process() CacheUnit* tlb_res = dynamic_cast<CacheUnit*>(resource); assert(tlb_res); + //@todo: eventually, we should do a timing translation w/ + // hw page table walk on tlb miss + DPRINTF(Fault, "Handling Fault %s\n", inst->fault->name()); + inst->fault->invoke(tlb_res->cpu->tcBase(tid), inst->staticInst); + tlb_res->tlbBlocked[tid] = false; tlb_res->cpu->pipelineStage[stage_num]-> |