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authorSteve Reinhardt <steve.reinhardt@amd.com>2015-02-11 10:48:50 -0800
committerSteve Reinhardt <steve.reinhardt@amd.com>2015-02-11 10:48:50 -0800
commitee0b52404c99cfed91a8d3fbebe3f42b0ac133df (patch)
tree5c26f8de53e57903f80ed45e643b4abd3020040a /src/cpu/inorder/resources/cache_unit.cc
parentccef61d1ccaea43cf44aa45bee272475f0b10405 (diff)
downloadgem5-ee0b52404c99cfed91a8d3fbebe3f42b0ac133df.tar.xz
mem: restructure Packet cmd initialization a bit more
Refactor the way that specific MemCmd values are generated for packets. The new approach is a little more elegant in that we assign the right value up front, and it's also more amenable to non-heap-allocated Packet objects. Also replaced the code in the Minor model that was still doing it the ad-hoc way. This is basically a refinement of http://repo.gem5.org/gem5/rev/711eb0e64249.
Diffstat (limited to 'src/cpu/inorder/resources/cache_unit.cc')
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc13
1 files changed, 10 insertions, 3 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index f8fa3b0d3..78b803501 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -811,10 +811,17 @@ CacheUnit::finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req)
void
CacheUnit::buildDataPacket(CacheRequest *cache_req)
{
- cache_req->dataPkt = new CacheReqPacket(cache_req,
- cache_req->pktCmd,
+ MemCmd cmd;
+
+ if (cache_req->pktCmd == MemCmd::ReadReq) {
+ cmd = Packet::makeReadCmd(cache_req->memReq);
+ } else {
+ assert(cache_req->pktCmd == MemCmd::WriteReq);
+ cmd = Packet::makeWriteCmd(cache_req->memReq);
+ }
+
+ cache_req->dataPkt = new CacheReqPacket(cache_req, cmd,
cache_req->instIdx);
- cache_req->dataPkt->refineCommand(); // handle LL/SC, etc.
DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x\n",
cache_req->getSlot(),