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author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
commit | 5127ea226a0a2cd75334c5af4cb182a1fd9b6cf1 (patch) | |
tree | 7ca2a867dd44c4c4b2e4d7de44ff04ec4cfd88c0 /src/cpu/inorder/resources/cache_unit.cc | |
parent | 98b1452058ae7e82df7cb7c0373c62a97981a2b9 (diff) | |
download | gem5-5127ea226a0a2cd75334c5af4cb182a1fd9b6cf1.tar.xz |
inorder-unified-tlb: use unified TLB instead of old TLB model
Diffstat (limited to 'src/cpu/inorder/resources/cache_unit.cc')
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 1b5d07450..6fe0bcf76 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -451,10 +451,12 @@ CacheUnit::processCacheCompletion(PacketPtr pkt) // Get resource request info - // @todo: SMT needs to figure out where to get thread # from. - unsigned tid = 0; unsigned stage_num = cache_req->getStageNum(); DynInstPtr inst = cache_req->inst; + unsigned tid; + + + tid = cache_req->inst->readTid(); if (!cache_req->isSquashed()) { if (inst->resSched.top()->cmd == CompleteFetch) { |