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author | Korey Sewell <ksewell@umich.edu> | 2011-02-18 14:27:52 -0500 |
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committer | Korey Sewell <ksewell@umich.edu> | 2011-02-18 14:27:52 -0500 |
commit | 991d0185c68b53a04ae5d1f1a05749bbfddced89 (patch) | |
tree | 70a97d5b52ff695810b00513a9b3e0907e2a5d4b /src/cpu/inorder/resources/cache_unit.cc | |
parent | 2971b8401a4a76a774962900d9aed6e9eb4b2950 (diff) | |
download | gem5-991d0185c68b53a04ae5d1f1a05749bbfddced89.tar.xz |
inorder: initialize res. req. vectors based on resource bandwidth
first change in an optimization that will stop InOrder from allocating new memory for every instruction's
request to a resource. This gets expensive since every instruction needs to access ~10 requests before
graduation. Instead, the plan is to allocate just enough resource request objects to satisfy each resource's
bandwidth (e.g. the execution unit would need to allocate 3 resource request objects for a 1-issue pipeline
since on any given cycle it could have 2 read requests and 1 write request) and then let the instructions
contend and reuse those allocated requests. The end result is a smaller memory footprint for the InOrder model
and increased simulation performance
Diffstat (limited to 'src/cpu/inorder/resources/cache_unit.cc')
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 8cd105493..47fafe45a 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -133,6 +133,11 @@ CacheUnit::getPort(const string &if_name, int idx) void CacheUnit::init() { + for (int i = 0; i < width; i++) { + reqs[i] = new CacheRequest(this, NULL, 0, 0, 0, 0, 0, + MemCmd::Command(0), 0, 0, 0); + } + // Currently Used to Model TLB Latency. Eventually // Switch to Timing TLB translations. resourceEvent = new CacheUnitEvent[width]; |