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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:40 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:40 -0400 |
| commit | f1c3691356355d2ca865e48e91814c56293f6326 (patch) | |
| tree | 6608284d5bcdab42d69042034d49198c647b1a2c /src/cpu/inorder/resources/cache_unit.cc | |
| parent | 0bfdf342da40842a05351d53a384db4a8ff88bf5 (diff) | |
| download | gem5-f1c3691356355d2ca865e48e91814c56293f6326.tar.xz | |
inorder: check for interrupts each tick
use a dummy instruction to facilitate the squash after
the interrupts trap
Diffstat (limited to 'src/cpu/inorder/resources/cache_unit.cc')
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index d0cdfa3c9..d21597aba 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -1248,7 +1248,8 @@ void CacheUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, ThreadID tid) { - if (tlbBlockSeqNum[tid] > squash_seq_num) { + if (tlbBlockSeqNum[tid] && + tlbBlockSeqNum[tid] > squash_seq_num) { DPRINTF(InOrderCachePort, "Releasing TLB Block due to " " squash after [sn:%i].\n", squash_seq_num); tlbBlocked[tid] = false; |