summaryrefslogtreecommitdiff
path: root/src/cpu/inorder/resources/cache_unit.hh
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-08-13 06:16:02 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-08-13 06:16:02 -0700
commitaa8c6e9c959eab4d516bc07593bea20ade9ad80c (patch)
tree3e0112e567da5dc1aa019f85458fbd9e37ad0cf2 /src/cpu/inorder/resources/cache_unit.hh
parent65dbcc6ea170e05ca2370a9a265a61668250fa98 (diff)
downloadgem5-aa8c6e9c959eab4d516bc07593bea20ade9ad80c.tar.xz
CPU: Add readBytes and writeBytes functions to the exec contexts.
Diffstat (limited to 'src/cpu/inorder/resources/cache_unit.hh')
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 177f81559..2f369db7c 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -161,12 +161,11 @@ class CacheUnit : public Resource
/** Returns a specific port. */
Port *getPort(const std::string &if_name, int idx);
- template <class T>
- Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags);
+ Fault read(DynInstPtr inst, Addr addr,
+ uint8_t *data, unsigned size, unsigned flags);
- template <class T>
- Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags,
- uint64_t *res);
+ Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
Fault doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
int flags, TheISA::TLB::Mode tlb_mode);