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| author | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:09:20 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:09:20 -0500 |
| commit | e396a34b0155d5054a099c67a91baa66c095d3d8 (patch) | |
| tree | 9372731b0110d067b4377ab73b1d62bbabf5efe3 /src/cpu/inorder/resources/cache_unit.hh | |
| parent | e57613588b15f25b5b912ae98134b6f1007988fd (diff) | |
| download | gem5-e396a34b0155d5054a099c67a91baa66c095d3d8.tar.xz | |
inorder: fault handling
Maintain all information about an instruction's fault in the DynInst object rather
than any cpu-request object. Also, if there is a fault during the execution stage
then just save the fault inside the instruction and trap once the instruction
tries to graduate
Diffstat (limited to 'src/cpu/inorder/resources/cache_unit.hh')
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh index 0d911999d..afcb36a24 100644 --- a/src/cpu/inorder/resources/cache_unit.hh +++ b/src/cpu/inorder/resources/cache_unit.hh @@ -161,13 +161,13 @@ class CacheUnit : public Resource Fault write(DynInstPtr inst, uint8_t *data, unsigned size, Addr addr, unsigned flags, uint64_t *res); - Fault doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size, + void doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size, int flags, TheISA::TLB::Mode tlb_mode); /** Read/Write on behalf of an instruction. * curResSlot needs to be a valid value in instruction. */ - Fault doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL, + void doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL, CacheReqPtr split_req=NULL); uint64_t getMemData(Packet *packet); |