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authorKorey Sewell <ksewell@umich.edu>2009-05-12 15:01:15 -0400
committerKorey Sewell <ksewell@umich.edu>2009-05-12 15:01:15 -0400
commitfe4cd9847db2b2d7d566a921670c92fa39d14136 (patch)
treea27928cb7e56f26cdd9bb34899d747ff0a91644f /src/cpu/inorder/resources/cache_unit.hh
parent6211fe5d2ee00dae9cd72d9cccdc900241a8f9a2 (diff)
downloadgem5-fe4cd9847db2b2d7d566a921670c92fa39d14136.tar.xz
inorder-stc: update interface to handle store conditionals
Diffstat (limited to 'src/cpu/inorder/resources/cache_unit.hh')
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 06ccf3bec..226a35a52 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -162,7 +162,7 @@ class CacheUnit : public Resource
/** Read/Write on behalf of an instruction.
* curResSlot needs to be a valid value in instruction.
*/
- Fault doDataAccess(DynInstPtr inst);
+ Fault doDataAccess(DynInstPtr inst, uint64_t *write_result=NULL);
void prefetch(DynInstPtr inst);
@@ -245,6 +245,8 @@ class CacheRequest : public ResourceRequest
memReq = inst->dataMemReq;
}
+ //@ Only matters for Fetch / Read requests
+ // Don't allocate for Writes!
reqData = new uint8_t[req_size];
retryPkt = NULL;
}