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author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:39 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:39 -0400 |
commit | 5f608dd2e9a760b4280fb03ce82a11a62c6f3af9 (patch) | |
tree | 725a942e67f2efeffaa84c4385afc81424e142ee /src/cpu/inorder/resources/cache_unit.hh | |
parent | e0e387c2a926dcdb53f85d8189e6d7158765b4ac (diff) | |
download | gem5-5f608dd2e9a760b4280fb03ce82a11a62c6f3af9.tar.xz |
inorder: squash and trap behind a tlb fault
Diffstat (limited to 'src/cpu/inorder/resources/cache_unit.hh')
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh index dd6fa7638..91a8703f7 100644 --- a/src/cpu/inorder/resources/cache_unit.hh +++ b/src/cpu/inorder/resources/cache_unit.hh @@ -203,9 +203,9 @@ class CacheUnit : public Resource } bool tlbBlocked[ThePipeline::MaxThreads]; + InstSeqNum tlbBlockSeqNum[ThePipeline::MaxThreads]; TheISA::TLB* tlb(); - TheISA::TLB *_tlb; }; |