CPU: Round-two unifying instr/data CPU ports across models

This patch continues the unification of how the different CPU models
create and share their instruction and data ports. Most importantly,
it forces every CPU to have an instruction and a data port, and gives
these ports explicit getters in the BaseCPU (getDataPort and
getInstPort). The patch helps in simplifying the code, make
assumptions more explicit, andfurther ease future patches related to
the CPU ports.

The biggest changes are in the in-order model (that was not modified
in the previous unification patch), which now moves the ports from the
CacheUnit to the CPU. It also distinguishes the instruction fetch and
load-store unit from the rest of the resources, and avoids the use of
indices and casting in favour of keeping track of these two units
explicitly (since they are always there anyways). The atomic, timing
and O3 model simply return references to their already existing ports.

1 files changed, 1 insertions, 37 deletions

diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 416cb76d1..d9f98e42c 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -73,39 +73,6 @@ class CacheUnit : public Resource
     };
 
   public:
-    /** CachePort class for the Cache Unit.  Handles doing the
-     * communication with the cache/memory.
-     */
-    class CachePort : public Port
-    {
-      protected:
-        /** Pointer to cache port unit */
-        CacheUnit *cachePortUnit;
-
-      public:
-        /** Default constructor. */
-        CachePort(CacheUnit *_cachePortUnit)
-          : Port(_cachePortUnit->name() + "-cache-port",
-                 (MemObject*)_cachePortUnit->cpu),
-            cachePortUnit(_cachePortUnit)
-        { }
-
-      protected:
-        /** Atomic version of receive.  Panics. */
-        Tick recvAtomic(PacketPtr pkt);
-
-        /** Functional version of receive.*/
-        void recvFunctional(PacketPtr pkt);
-
-        /** Receives range changes. */
-        void recvRangeChange();
-
-        /** Timing version of receive */
-        bool recvTiming(PacketPtr pkt);
-
-        /** Handles doing a retry of a failed fetch. */
-        void recvRetry();
-    };
 
     void init();
 
@@ -149,9 +116,6 @@ class CacheUnit : public Resource
     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 
     void recvRetry();
-
-    /** Returns a specific port. */
-    Port *getPort(const std::string &if_name, int idx);
     
     Fault read(DynInstPtr inst, Addr addr,
                uint8_t *data, unsigned size, unsigned flags);
@@ -175,7 +139,7 @@ class CacheUnit : public Resource
     
   protected:
     /** Cache interface. */
-    CachePort *cachePort;
+    Port *cachePort;
 
     bool cachePortBlocked;