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| author | Korey Sewell <ksewell@umich.edu> | 2010-06-24 15:34:12 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2010-06-24 15:34:12 -0400 |
| commit | f95430d97e0a9a77b920ab3ca24b134bc682f655 (patch) | |
| tree | 13a5424847b8e4a65135e82a518ef60ed069b2d3 /src/cpu/inorder/resources/cache_unit.hh | |
| parent | ecba3074c2eb9e873655a1e0e49bfd03e2bd2a41 (diff) | |
| download | gem5-f95430d97e0a9a77b920ab3ca24b134bc682f655.tar.xz | |
inorder: enforce 78-character rule
Diffstat (limited to 'src/cpu/inorder/resources/cache_unit.hh')
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh index 9004f3b93..7e3052bd7 100644 --- a/src/cpu/inorder/resources/cache_unit.hh +++ b/src/cpu/inorder/resources/cache_unit.hh @@ -174,7 +174,8 @@ class CacheUnit : public Resource /** Read/Write on behalf of an instruction. * curResSlot needs to be a valid value in instruction. */ - Fault doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL, CacheReqPtr split_req=NULL); + Fault doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL, + CacheReqPtr split_req=NULL); void prefetch(DynInstPtr inst); |