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authorKorey Sewell <ksewell@umich.edu>2009-03-04 13:17:09 -0500
committerKorey Sewell <ksewell@umich.edu>2009-03-04 13:17:09 -0500
commit7c8d54421665ccbc204487cb6a9faa31c1b3c243 (patch)
treecb7fccabb1f88bb8567575ff20125b183fb645df /src/cpu/inorder/resources/decode_unit.cc
parent30cd2d21fad6c12e2540672f315f561c9a1643ec (diff)
downloadgem5-7c8d54421665ccbc204487cb6a9faa31c1b3c243.tar.xz
Give each resource in InOrder it's own TraceFlag instead of just standard 'Resource' flag
Diffstat (limited to 'src/cpu/inorder/resources/decode_unit.cc')
-rw-r--r--src/cpu/inorder/resources/decode_unit.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/inorder/resources/decode_unit.cc b/src/cpu/inorder/resources/decode_unit.cc
index 1628c32d0..d95b1d4bb 100644
--- a/src/cpu/inorder/resources/decode_unit.cc
+++ b/src/cpu/inorder/resources/decode_unit.cc
@@ -63,7 +63,7 @@ DecodeUnit::execute(int slot_num)
bool done_sked = ThePipeline::createBackEndSchedule(inst);
if (done_sked) {
- DPRINTF(Resource, "[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
+ DPRINTF(InOrderDecode, "[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
tid, seq_num);
regDepMap[tid]->insert(inst);
decode_req->done();
@@ -85,7 +85,7 @@ DecodeUnit::execute(int slot_num)
void
DecodeUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid)
{
- DPRINTF(Resource, "[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
+ DPRINTF(InOrderDecode, "[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
tid, stage_num, squash_seq_num);
//cpu->removeInstsUntil(squash_seq_num, tid);