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| author | Korey Sewell <ksewell@umich.edu> | 2009-03-04 13:17:09 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-03-04 13:17:09 -0500 |
| commit | 7c8d54421665ccbc204487cb6a9faa31c1b3c243 (patch) | |
| tree | cb7fccabb1f88bb8567575ff20125b183fb645df /src/cpu/inorder/resources/execution_unit.cc | |
| parent | 30cd2d21fad6c12e2540672f315f561c9a1643ec (diff) | |
| download | gem5-7c8d54421665ccbc204487cb6a9faa31c1b3c243.tar.xz | |
Give each resource in InOrder it's own TraceFlag instead of just standard 'Resource' flag
Diffstat (limited to 'src/cpu/inorder/resources/execution_unit.cc')
| -rw-r--r-- | src/cpu/inorder/resources/execution_unit.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc index e41291103..843adb5b0 100644 --- a/src/cpu/inorder/resources/execution_unit.cc +++ b/src/cpu/inorder/resources/execution_unit.cc @@ -68,7 +68,7 @@ ExecutionUnit::execute(int slot_num) exec_req->fault = NoFault; - DPRINTF(Resource, "[tid:%i] Executing [sn:%i] [PC:%#x] .\n", + DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] .\n", tid, seq_num, inst->readPC()); switch (exec_req->cmd) @@ -99,7 +99,7 @@ ExecutionUnit::execute(int slot_num) inst->bdelaySeqNum = seq_num; inst->setPredTarg(inst->nextPC); - DPRINTF(Resource, "[tid:%i]: Conditional branch inst" + DPRINTF(InOrderExecute, "[tid:%i]: Conditional branch inst" "[sn:%i] PC %#x mispredicted as taken.\n", tid, seq_num, inst->PC); } else if (!inst->predTaken() && inst->isCondDelaySlot()) { @@ -107,13 +107,13 @@ ExecutionUnit::execute(int slot_num) inst->setPredTarg(inst->nextPC); inst->procDelaySlotOnMispred = true; - DPRINTF(Resource, "[tid:%i]: Conditional branch inst." + DPRINTF(InOrderExecute, "[tid:%i]: Conditional branch inst." "[sn:%i] PC %#x mispredicted as not taken.\n", tid, seq_num, inst->PC); } else { inst->bdelaySeqNum = seq_num + 1; - DPRINTF(Resource, "[tid:%i]: Misprediction detected at " + DPRINTF(InOrderExecute, "[tid:%i]: Misprediction detected at " "[sn:%i] PC %#x,\n\t squashing after delay slot " "instruction [sn:%i].\n", tid, seq_num, inst->PC, inst->bdelaySeqNum); @@ -122,20 +122,20 @@ ExecutionUnit::execute(int slot_num) inst->setPredTarg(inst->nextNPC); } - DPRINTF(Resource, "[tid:%i] Redirecting fetch to %#x.\n", tid, + DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid, inst->readPredTarg()); } else if(inst->isIndirectCtrl()){ inst->setPredTarg(inst->nextNPC); inst->bdelaySeqNum = seq_num + 1; - DPRINTF(Resource, "[tid:%i] Redirecting fetch to %#x.\n", tid, + DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid, inst->readPredTarg()); } else { panic("Non-control instruction (%s) mispredicting?!!", inst->staticInst->getName()); } - DPRINTF(Resource, "[tid:%i] Squashing will start from stage %i.\n", + DPRINTF(InOrderExecute, "[tid:%i] Squashing will start from stage %i.\n", tid, stage_num); cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid); @@ -164,7 +164,7 @@ ExecutionUnit::execute(int slot_num) inst->setExecuted(); exec_req->done(); - DPRINTF(Resource, "[tid:%i]: The result of execution is 0x%x.\n", + DPRINTF(InOrderExecute, "[tid:%i]: The result of execution is 0x%x.\n", inst->readTid(), inst->readIntResult(0)); } else { warn("inst [sn:%i] had a %s fault", seq_num, fault->name()); |