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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
| commit | b569f8f0ed8dcf32347f0d4f68d2d7572a5d1353 (patch) | |
| tree | 14b4f11266600c44ec4c1846665277115911b363 /src/cpu/inorder/resources/execution_unit.cc | |
| parent | 1c8dfd92543aba5f49e464b17e7e8143fc01a58c (diff) | |
| download | gem5-b569f8f0ed8dcf32347f0d4f68d2d7572a5d1353.tar.xz | |
inorder-bpred: edits to handle non-delay-slot ISAs
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
Diffstat (limited to 'src/cpu/inorder/resources/execution_unit.cc')
| -rw-r--r-- | src/cpu/inorder/resources/execution_unit.cc | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc index 843adb5b0..60cbac8af 100644 --- a/src/cpu/inorder/resources/execution_unit.cc +++ b/src/cpu/inorder/resources/execution_unit.cc @@ -76,7 +76,7 @@ ExecutionUnit::execute(int slot_num) case ExecuteInst: { if (inst->isMemRef()) { - fatal("%s not configured to handle memory ops.\n", resName); + panic("%s not configured to handle memory ops.\n", resName); } else if (inst->isControl()) { // Evaluate Branch fault = inst->execute(); @@ -111,23 +111,33 @@ ExecutionUnit::execute(int slot_num) "[sn:%i] PC %#x mispredicted as not taken.\n", tid, seq_num, inst->PC); } else { +#if ISA_HAS_DELAY_SLOT inst->bdelaySeqNum = seq_num + 1; - + inst->setPredTarg(inst->nextNPC); +#else + inst->bdelaySeqNum = seq_num; + inst->setPredTarg(inst->nextPC); +#endif DPRINTF(InOrderExecute, "[tid:%i]: Misprediction detected at " "[sn:%i] PC %#x,\n\t squashing after delay slot " "instruction [sn:%i].\n", tid, seq_num, inst->PC, inst->bdelaySeqNum); DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch " "misprediction at %#x\n", tid, inst->PC); - inst->setPredTarg(inst->nextNPC); } DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid, inst->readPredTarg()); } else if(inst->isIndirectCtrl()){ +#if ISA_HAS_DELAY_SLOT inst->setPredTarg(inst->nextNPC); inst->bdelaySeqNum = seq_num + 1; +#else + inst->setPredTarg(inst->nextPC); + inst->bdelaySeqNum = seq_num; +#endif + DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid, inst->readPredTarg()); } else { @@ -151,7 +161,13 @@ ExecutionUnit::execute(int slot_num) } else { predictedNotTakenIncorrect++; } + } else { + DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction Correct.\n", + inst->readTid(), seq_num, inst->readIntResult(0)); } + + DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n", + inst->readTid(), seq_num, inst->readIntResult(0)); exec_req->done(); } else { warn("inst [sn:%i] had a %s fault", seq_num, fault->name()); @@ -164,8 +180,8 @@ ExecutionUnit::execute(int slot_num) inst->setExecuted(); exec_req->done(); - DPRINTF(InOrderExecute, "[tid:%i]: The result of execution is 0x%x.\n", - inst->readTid(), inst->readIntResult(0)); + DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n", + inst->readTid(), seq_num, inst->readIntResult(0)); } else { warn("inst [sn:%i] had a %s fault", seq_num, fault->name()); cpu->trap(fault, tid); |