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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
| commit | b569f8f0ed8dcf32347f0d4f68d2d7572a5d1353 (patch) | |
| tree | 14b4f11266600c44ec4c1846665277115911b363 /src/cpu/inorder/resources/fetch_seq_unit.cc | |
| parent | 1c8dfd92543aba5f49e464b17e7e8143fc01a58c (diff) | |
| download | gem5-b569f8f0ed8dcf32347f0d4f68d2d7572a5d1353.tar.xz | |
inorder-bpred: edits to handle non-delay-slot ISAs
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
Diffstat (limited to 'src/cpu/inorder/resources/fetch_seq_unit.cc')
| -rw-r--r-- | src/cpu/inorder/resources/fetch_seq_unit.cc | 36 |
1 files changed, 25 insertions, 11 deletions
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc index 444252e1b..69610ae58 100644 --- a/src/cpu/inorder/resources/fetch_seq_unit.cc +++ b/src/cpu/inorder/resources/fetch_seq_unit.cc @@ -96,13 +96,16 @@ FetchSeqUnit::execute(int slot_num) inst->setNextPC(PC[tid] + instSize); inst->setNextNPC(PC[tid] + (instSize * 2)); +#if ISA_HAS_DELAY_SLOT inst->setPredTarg(inst->readNextNPC()); - +#else + inst->setPredTarg(inst->readNextPC()); +#endif inst->setMemAddr(PC[tid]); inst->setSeqNum(cpu->getAndIncrementInstSeq(tid)); - DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to PC %08p\n", tid, - inst->seqNum, inst->readPC()); + DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to PC %08p, NPC %08p, NNPC %08p\n", tid, + inst->seqNum, inst->readPC(), inst->readNextPC(), inst->readNextNPC()); if (delaySlotInfo[tid].numInsts > 0) { --delaySlotInfo[tid].numInsts; @@ -150,30 +153,37 @@ FetchSeqUnit::execute(int slot_num) squashAfterInst(inst, stage_num, tid); } else if (!inst->isCondDelaySlot() && !inst->predTaken()) { - // Not-Taken Control + // Not-Taken Control DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted Not-Taken Control " "inst. updating PC to %08p\n", tid, inst->seqNum, inst->readNextPC()); - +#if ISA_HAS_DELAY_SLOT ++delaySlotInfo[tid].numInsts; delaySlotInfo[tid].targetReady = false; delaySlotInfo[tid].targetAddr = inst->readNextNPC(); - +#else + assert(delaySlotInfo[tid].numInsts == 0); +#endif } else if (inst->predTaken()) { - // Taken Control + // Taken Control +#if ISA_HAS_DELAY_SLOT ++delaySlotInfo[tid].numInsts; delaySlotInfo[tid].targetReady = false; delaySlotInfo[tid].targetAddr = inst->readPredTarg(); DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay slot target " "to PC %08p\n", tid, inst->seqNum, inst->readPredTarg()); - - // Set-Up Squash Through-Out Pipeline - DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n", - tid, stage_num, seq_num + 1); inst->bdelaySeqNum = seq_num + 1; +#else + inst->bdelaySeqNum = seq_num; + assert(delaySlotInfo[tid].numInsts == 0); +#endif + inst->squashingStage = stage_num; + DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n", + tid, stage_num, inst->bdelaySeqNum); + // Do Squashing squashAfterInst(inst, stage_num, tid); } @@ -239,6 +249,10 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage, DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]); } else { +#if !ISA_HAS_DELAY_SLOT + assert(0); +#endif + delaySlotInfo[tid].numInsts = 1; delaySlotInfo[tid].targetReady = false; delaySlotInfo[tid].targetAddr = (inst->procDelaySlotOnMispred) ? inst->branchTarget() : new_PC; |