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author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:40 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:40 -0400 |
commit | 561c33f0824a705cb360ecb4ae3bf8cfd490f007 (patch) | |
tree | 7fb92ebc9a8f09ceacb8ad8e60e60990a9939621 /src/cpu/inorder/resources/fetch_unit.cc | |
parent | c4deabfb97928f81acb0d66338426cb5f2687c37 (diff) | |
download | gem5-561c33f0824a705cb360ecb4ae3bf8cfd490f007.tar.xz |
inorder: dont handle multiple faults on same cycle
if a faulting instruction reaches an execution unit,
then ignore it and pass it through the pipeline.
Once we recognize the fault in the graduation unit,
dont allow a second fault to creep in on the same cycle.
Diffstat (limited to 'src/cpu/inorder/resources/fetch_unit.cc')
-rw-r--r-- | src/cpu/inorder/resources/fetch_unit.cc | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc index 958d69b34..85411ae28 100644 --- a/src/cpu/inorder/resources/fetch_unit.cc +++ b/src/cpu/inorder/resources/fetch_unit.cc @@ -247,7 +247,14 @@ FetchUnit::execute(int slot_num) Addr block_addr = cacheBlockAlign(inst->getMemAddr()); int asid = cpu->asid[tid]; - inst->fault = NoFault; + if (inst->fault != NoFault) { + DPRINTF(InOrderCachePort, + "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to " + "next stage.\n", tid, inst->seqNum, inst->fault->name(), + cacheBlockAlign(inst->getMemAddr())); + finishCacheUnitReq(inst, cache_req); + return; + } switch (cache_req->cmd) { @@ -295,7 +302,7 @@ FetchUnit::execute(int slot_num) return; } - doTLBAccess(inst, cache_req, cacheBlkSize, 0, TheISA::TLB::Execute); + doTLBAccess(inst, cache_req, cacheBlkSize, Request::INST_FETCH, TheISA::TLB::Execute); if (inst->fault == NoFault) { DPRINTF(InOrderCachePort, @@ -320,6 +327,15 @@ FetchUnit::execute(int slot_num) } case CompleteFetch: + if (inst->fault != NoFault) { + DPRINTF(InOrderCachePort, + "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to " + "next stage.\n", tid, inst->seqNum, inst->fault->name(), + inst->getMemAddr()); + finishCacheUnitReq(inst, cache_req); + return; + } + if (cache_req->fetchBufferFill) { // Block request if it's depending on a previous fetch, but it hasnt made it yet std::list<FetchBlock*>::iterator fetch_it = findBlock(fetchBuffer, asid, block_addr); |