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| author | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:09:20 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:09:20 -0500 |
| commit | e396a34b0155d5054a099c67a91baa66c095d3d8 (patch) | |
| tree | 9372731b0110d067b4377ab73b1d62bbabf5efe3 /src/cpu/inorder/resources/fetch_unit.cc | |
| parent | e57613588b15f25b5b912ae98134b6f1007988fd (diff) | |
| download | gem5-e396a34b0155d5054a099c67a91baa66c095d3d8.tar.xz | |
inorder: fault handling
Maintain all information about an instruction's fault in the DynInst object rather
than any cpu-request object. Also, if there is a fault during the execution stage
then just save the fault inside the instruction and trap once the instruction
tries to graduate
Diffstat (limited to 'src/cpu/inorder/resources/fetch_unit.cc')
| -rw-r--r-- | src/cpu/inorder/resources/fetch_unit.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc index 7bbeffadd..0e9866708 100644 --- a/src/cpu/inorder/resources/fetch_unit.cc +++ b/src/cpu/inorder/resources/fetch_unit.cc @@ -227,7 +227,8 @@ FetchUnit::execute(int slot_num) ThreadID tid = inst->readTid(); Addr block_addr = cacheBlockAlign(inst->getMemAddr()); int asid = cpu->asid[tid]; - cache_req->fault = NoFault; + + inst->fault = NoFault; switch (cache_req->cmd) { @@ -275,7 +276,7 @@ FetchUnit::execute(int slot_num) doTLBAccess(inst, cache_req, cacheBlkSize, 0, TheISA::TLB::Execute); - if (cache_req->fault == NoFault) { + if (inst->fault == NoFault) { DPRINTF(InOrderCachePort, "[tid:%u]: Initiating fetch access to %s for " "addr:%#x (block:%#x)\n", tid, name(), |