diff options
| author | Korey Sewell <ksewell@umich.edu> | 2011-02-12 10:14:45 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-02-12 10:14:45 -0500 |
| commit | e26aee514d328bd8c9930c742df6ce1485dce5ae (patch) | |
| tree | d64c361532c00a47d30ddcb58b3205406b1adfe4 /src/cpu/inorder/resources/fetch_unit.cc | |
| parent | 516b61146271b13d2350563b0349747724ffbc99 (diff) | |
| download | gem5-e26aee514d328bd8c9930c742df6ce1485dce5ae.tar.xz | |
inorder: utilize cached skeds in pipeline
allow the pipeline and resources to use the cached instruction schedule and resource
sked iterator
Diffstat (limited to 'src/cpu/inorder/resources/fetch_unit.cc')
| -rw-r--r-- | src/cpu/inorder/resources/fetch_unit.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc index 0e9866708..0a5483aff 100644 --- a/src/cpu/inorder/resources/fetch_unit.cc +++ b/src/cpu/inorder/resources/fetch_unit.cc @@ -118,7 +118,7 @@ ResReqPtr FetchUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx, int slot_num, unsigned cmd) { - ScheduleEntry* sched_entry = inst->resSched.top(); + ScheduleEntry* sched_entry = *inst->curSkedEntry; if (!inst->validMemAddr()) { panic("Mem. Addr. must be set before requesting cache access\n"); @@ -144,7 +144,7 @@ FetchUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx, return new CacheRequest(this, inst, stage_num, id, slot_num, sched_entry->cmd, 0, pkt_cmd, 0/*flags*/, this->cpu->readCpuId(), - inst->resSched.top()->idx); + inst->curSkedEntry->idx); } void @@ -447,7 +447,7 @@ FetchUnit::processCacheCompletion(PacketPtr pkt) short asid = cpu->asid[tid]; assert(!cache_req->isSquashed()); - assert(inst->resSched.top()->cmd == CompleteFetch); + assert(inst->curSkedEntry->cmd == CompleteFetch); DPRINTF(InOrderCachePort, "[tid:%u]: [sn:%i]: Processing fetch access for block %#x\n", |