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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:15 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:15 -0400 |
| commit | 1c7e988272efead94d2cfbe3fd65ba454d3e1fc1 (patch) | |
| tree | 55affa4470c6cc8cdadc8da953895a0b3a163a24 /src/cpu/inorder/resources/tlb_unit.cc | |
| parent | f41df0ee08467711c613faadf9879052ab7196ed (diff) | |
| download | gem5-1c7e988272efead94d2cfbe3fd65ba454d3e1fc1.tar.xz | |
inorder-mem: skeleton support for prefetch/writehints
Diffstat (limited to 'src/cpu/inorder/resources/tlb_unit.cc')
| -rw-r--r-- | src/cpu/inorder/resources/tlb_unit.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc index dbf799661..8532a30ed 100644 --- a/src/cpu/inorder/resources/tlb_unit.cc +++ b/src/cpu/inorder/resources/tlb_unit.cc @@ -158,8 +158,8 @@ TLBUnit::execute(int slot_idx) if (tlb_req->fault != NoFault) { DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating " - "addr:%08p for [sn:%i].\n", tid, tlb_req->fault->name(), - tlb_req->memReq->getVaddr(), seq_num); + "addr:%08p for [sn:%i] %s.\n", tid, tlb_req->fault->name(), + tlb_req->memReq->getVaddr(), seq_num, inst->instName()); //insert(inst); cpu->pipelineStage[stage_num]->setResStall(tlb_req, tid); tlbBlocked[tid] = true; |