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authorKorey Sewell <ksewell@umich.edu>2009-05-12 15:01:15 -0400
committerKorey Sewell <ksewell@umich.edu>2009-05-12 15:01:15 -0400
commit6211fe5d2ee00dae9cd72d9cccdc900241a8f9a2 (patch)
treeee0ac43983c31c9c22b7ea28e69725d033287ef4 /src/cpu/inorder/resources/tlb_unit.cc
parent3603dd25efb70ec400e8ea1e76137e8e288e533a (diff)
downloadgem5-6211fe5d2ee00dae9cd72d9cccdc900241a8f9a2.tar.xz
inorder-float: Fix storage of FP results
inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from the actual floating point register file, the model can figure out what it needs to store
Diffstat (limited to 'src/cpu/inorder/resources/tlb_unit.cc')
-rw-r--r--src/cpu/inorder/resources/tlb_unit.cc13
1 files changed, 7 insertions, 6 deletions
diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index 8532a30ed..238807ebc 100644
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -160,13 +160,14 @@ TLBUnit::execute(int slot_idx)
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
"addr:%08p for [sn:%i] %s.\n", tid, tlb_req->fault->name(),
tlb_req->memReq->getVaddr(), seq_num, inst->instName());
- //insert(inst);
- cpu->pipelineStage[stage_num]->setResStall(tlb_req, tid);
- tlbBlocked[tid] = true;
- scheduleEvent(slot_idx, 1);
- // Let CPU handle the fault
- cpu->trap(tlb_req->fault, tid);
+ cpu->pipelineStage[stage_num]->setResStall(tlb_req, tid);
+ tlbBlocked[tid] = true;
+ scheduleEvent(slot_idx, 1);
+
+ // Let CPU handle the fault
+ cpu->trap(tlb_req->fault, tid);
+
} else {
DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
"to phys. addr:%08p.\n", tid, seq_num,