diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
commit | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch) | |
tree | 0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/cpu/inorder/resources/tlb_unit.hh | |
parent | 7e104a1af235823e3d641a972ea920937f7ec67d (diff) | |
download | gem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Diffstat (limited to 'src/cpu/inorder/resources/tlb_unit.hh')
-rw-r--r-- | src/cpu/inorder/resources/tlb_unit.hh | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh index caccb5a9f..6846bdc87 100644 --- a/src/cpu/inorder/resources/tlb_unit.hh +++ b/src/cpu/inorder/resources/tlb_unit.hh @@ -118,7 +118,9 @@ class TLBUnitRequest : public ResourceRequest { req_size = sizeof(TheISA::MachInst); flags = 0; inst->fetchMemReq = new Request(inst->readTid(), aligned_addr, - req_size, flags, inst->instAddr(), + req_size, flags, + res->cpu->instMasterId(), + inst->instAddr(), res->cpu->readCpuId(), inst->readTid()); memReq = inst->fetchMemReq; @@ -132,7 +134,9 @@ class TLBUnitRequest : public ResourceRequest { } inst->dataMemReq = new Request(inst->readTid(), aligned_addr, - req_size, flags, inst->instAddr(), + req_size, flags, + res->cpu->dataMasterId(), + inst->instAddr(), res->cpu->readCpuId(), inst->readTid()); memReq = inst->dataMemReq; |