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authorKorey Sewell <ksewell@umich.edu>2009-05-12 15:01:14 -0400
committerKorey Sewell <ksewell@umich.edu>2009-05-12 15:01:14 -0400
commit5127ea226a0a2cd75334c5af4cb182a1fd9b6cf1 (patch)
tree7ca2a867dd44c4c4b2e4d7de44ff04ec4cfd88c0 /src/cpu/inorder/resources/tlb_unit.hh
parent98b1452058ae7e82df7cb7c0373c62a97981a2b9 (diff)
downloadgem5-5127ea226a0a2cd75334c5af4cb182a1fd9b6cf1.tar.xz
inorder-unified-tlb: use unified TLB instead of old TLB model
Diffstat (limited to 'src/cpu/inorder/resources/tlb_unit.hh')
-rw-r--r--src/cpu/inorder/resources/tlb_unit.hh5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh
index b53f251fc..b0cdac2a2 100644
--- a/src/cpu/inorder/resources/tlb_unit.hh
+++ b/src/cpu/inorder/resources/tlb_unit.hh
@@ -47,7 +47,8 @@ class TLBUnit : public InstBuffer {
enum TLBCommand {
FetchLookup,
- DataLookup
+ DataReadLookup,
+ DataWriteLookup
};
public:
@@ -103,7 +104,7 @@ class TLBUnitRequest : public ResourceRequest {
if (_cmd == TLBUnit::FetchLookup) {
aligned_addr = inst->getMemAddr();
- req_size = sizeof(MachInst);
+ req_size = sizeof(TheISA::MachInst);
flags = 0;
} else {
aligned_addr = inst->getMemAddr();;