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author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:40 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:40 -0400 |
commit | 561c33f0824a705cb360ecb4ae3bf8cfd490f007 (patch) | |
tree | 7fb92ebc9a8f09ceacb8ad8e60e60990a9939621 /src/cpu/inorder/resources/use_def.cc | |
parent | c4deabfb97928f81acb0d66338426cb5f2687c37 (diff) | |
download | gem5-561c33f0824a705cb360ecb4ae3bf8cfd490f007.tar.xz |
inorder: dont handle multiple faults on same cycle
if a faulting instruction reaches an execution unit,
then ignore it and pass it through the pipeline.
Once we recognize the fault in the graduation unit,
dont allow a second fault to creep in on the same cycle.
Diffstat (limited to 'src/cpu/inorder/resources/use_def.cc')
-rw-r--r-- | src/cpu/inorder/resources/use_def.cc | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc index 78497f6e5..06591121e 100644 --- a/src/cpu/inorder/resources/use_def.cc +++ b/src/cpu/inorder/resources/use_def.cc @@ -92,6 +92,9 @@ UseDefUnit::regStats() .desc("Total Accesses (Read+Write) to the FP Register File"); floatRegFileAccs = floatRegFileReads + floatRegFileWrites; + //@todo: add miscreg reads/writes + // add forwarding by type??? + regForwards .name(name() + ".regForwards") .desc("Number of Registers Read Through Forwarding Logic"); @@ -153,12 +156,19 @@ UseDefUnit::execute(int slot_idx) // for performance considerations UseDefRequest* ud_req = dynamic_cast<UseDefRequest*>(reqs[slot_idx]); assert(ud_req); - DynInstPtr inst = ud_req->inst; + if (inst->fault != NoFault) { + DPRINTF(InOrderUseDef, + "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to " + "next stage.\n", inst->readTid(), inst->seqNum, inst->fault->name(), + inst->pcState()); + ud_req->done(); + return; + } + ThreadID tid = inst->readTid(); InstSeqNum seq_num = inst->seqNum; int ud_idx = ud_req->useDefIdx; - // If there is a non-speculative instruction // in the pipeline then stall instructions here if (*nonSpecInstActive[tid] == true && seq_num > *nonSpecSeqNum[tid]) { |