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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:42 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:42 -0400 |
| commit | fe3a2aa4a31756d71440d25b2fe8fcc2f8ca4c67 (patch) | |
| tree | f2b1dc351d5f58dbe7b3f06d8aa8c96754142645 /src/cpu/inorder/resources | |
| parent | e572c01120fce6502d31f17a91f4bb83c6f9c3fe (diff) | |
| download | gem5-fe3a2aa4a31756d71440d25b2fe8fcc2f8ca4c67.tar.xz | |
inorder: se compile fixes
Diffstat (limited to 'src/cpu/inorder/resources')
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 94f2d0461..350e2d1dd 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -454,8 +454,8 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size, // schedule a time to process the tlb miss. // latency hardcoded to 1 (for now), but will be updated // when timing translation gets added in - scheduleEvent(slot_idx, 1); unsigned slot_idx = cache_req->getSlot(); + scheduleEvent(slot_idx, 1); #endif // Mark it as complete so it can pass through next stage. |