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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
| commit | f85286b3debf4a4a94d3b959e5bb880be81bd692 (patch) | |
| tree | 56a6be55a52d6cc6bb7e5d92fdcb25c79ad7d196 /src/cpu/inorder/resources | |
| parent | 06c39a154c4dc8fedcf9fbf77bbcf26f176c469c (diff) | |
| download | gem5-f85286b3debf4a4a94d3b959e5bb880be81bd692.tar.xz | |
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'src/cpu/inorder/resources')
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 15 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.hh | 2 |
2 files changed, 0 insertions, 17 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 73dd9c527..7fcab6893 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -145,21 +145,6 @@ CacheUnit::tlb() } -void -CacheUnit::CachePort::setPeer(Port *port) -{ - Port::setPeer(port); - -#if FULL_SYSTEM - // Update the ThreadContext's memory ports (Functional/Virtual - // Ports) - if (cachePortUnit->resName == "dcache_port") { - cachePortUnit->cpu->updateMemPorts(); - } - -#endif -} - Port * CacheUnit::getPort(const string &if_name, int idx) { diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh index 6bb5868b1..78eff9991 100644 --- a/src/cpu/inorder/resources/cache_unit.hh +++ b/src/cpu/inorder/resources/cache_unit.hh @@ -95,8 +95,6 @@ class CacheUnit : public Resource bool snoopRangeSent; - void setPeer(Port *port); - protected: /** Atomic version of receive. Panics. */ Tick recvAtomic(PacketPtr pkt); |