ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.

This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.

8 files changed, 195 insertions, 263 deletions

diff --git a/src/cpu/inorder/resources/bpred_unit.cc b/src/cpu/inorder/resources/bpred_unit.cc
index b08a393f7..310053409 100644
--- a/src/cpu/inorder/resources/bpred_unit.cc
+++ b/src/cpu/inorder/resources/bpred_unit.cc
@@ -31,6 +31,7 @@
 #include <list>
 #include <vector>
 
+#include "arch/utility.hh"
 #include "base/trace.hh"
 #include "base/traceflags.hh"
 #include "config/the_isa.hh"
@@ -149,7 +150,7 @@ BPredUnit::takeOverFrom()
 
 
 bool
-BPredUnit::predict(DynInstPtr &inst, Addr &pred_PC, ThreadID tid)
+BPredUnit::predict(DynInstPtr &inst, TheISA::PCState &predPC, ThreadID tid)
 {
     // See if branch predictor predicts taken.
     // If so, get its target addr either from the BTB or the RAS.
@@ -160,12 +161,13 @@ BPredUnit::predict(DynInstPtr &inst, Addr &pred_PC, ThreadID tid)
     
     int asid = inst->asid;
     bool pred_taken = false;
-    Addr target;
+    TheISA::PCState target;
 
     ++lookups;
-    DPRINTF(InOrderBPred, "[tid:%i] [sn:%i] %s ... PC%#x doing branch "
+    DPRINTF(InOrderBPred, "[tid:%i] [sn:%i] %s ... PC %s doing branch "
             "prediction\n", tid, inst->seqNum,
-            inst->staticInst->disassemble(inst->PC), inst->readPC());
+            inst->staticInst->disassemble(inst->instAddr()),
+            inst->pcState());
 
 
     void *bp_history = NULL;
@@ -185,14 +187,14 @@ BPredUnit::predict(DynInstPtr &inst, Addr &pred_PC, ThreadID tid)
     } else {
         ++condPredicted;
 
-        pred_taken = BPLookup(pred_PC, bp_history);
+        pred_taken = BPLookup(predPC.instAddr(), bp_history);
 
         DPRINTF(InOrderBPred, "[tid:%i]: Branch predictor predicted %i "
-                "for PC %#x\n",
-                tid, pred_taken, inst->readPC());
+                "for PC %s\n",
+                tid, pred_taken, inst->pcState());
     }
 
-    PredictorHistory predict_record(inst->seqNum, pred_PC, pred_taken,
+    PredictorHistory predict_record(inst->seqNum, predPC, pred_taken,
                                     bp_history, tid);
 
     // Now lookup in the BTB or RAS.
@@ -202,40 +204,37 @@ BPredUnit::predict(DynInstPtr &inst, Addr &pred_PC, ThreadID tid)
 
             // If it's a function return call, then look up the address
             // in the RAS.
-            target = RAS[tid].top();
+            TheISA::PCState rasTop = RAS[tid].top();
+            target = TheISA::buildRetPC(inst->pcState(), rasTop);
 
             // Record the top entry of the RAS, and its index.
             predict_record.usedRAS = true;
             predict_record.RASIndex = RAS[tid].topIdx();
-            predict_record.RASTarget = target;
+            predict_record.rasTarget = rasTop;
 
             assert(predict_record.RASIndex < 16);
 
             RAS[tid].pop();
 
-            DPRINTF(InOrderBPred, "[tid:%i]: Instruction %#x is a return, "
-                    "RAS predicted target: %#x, RAS index: %i.\n",
-                    tid, inst->readPC(), target, predict_record.RASIndex);
+            DPRINTF(InOrderBPred, "[tid:%i]: Instruction %s is a return, "
+                    "RAS predicted target: %s, RAS index: %i.\n",
+                    tid, inst->pcState(), target,
+                    predict_record.RASIndex);
         } else {
             ++BTBLookups;
 
             if (inst->isCall()) {
 
-#if ISA_HAS_DELAY_SLOT
-                Addr ras_pc = pred_PC + instSize; // Next Next PC
-#else
-                Addr ras_pc = pred_PC; // Next PC
-#endif
-
-                RAS[tid].push(ras_pc);
+                RAS[tid].push(inst->pcState());
 
                 // Record that it was a call so that the top RAS entry can
                 // be popped off if the speculation is incorrect.
                 predict_record.wasCall = true;
 
-                DPRINTF(InOrderBPred, "[tid:%i]: Instruction %#x was a call"
-                        ", adding %#x to the RAS index: %i.\n",
-                        tid, inst->readPC(), ras_pc, RAS[tid].topIdx());
+                DPRINTF(InOrderBPred, "[tid:%i]: Instruction %s was a call"
+                        ", adding %s to the RAS index: %i.\n",
+                        tid, inst->pcState(), predPC,
+                        RAS[tid].topIdx());
             }
 
             if (inst->isCall() &&
@@ -243,18 +242,18 @@ BPredUnit::predict(DynInstPtr &inst, Addr &pred_PC, ThreadID tid)
                 inst->isDirectCtrl()) {
                 target = inst->branchTarget();
 
-                DPRINTF(InOrderBPred, "[tid:%i]: Setting %#x predicted"
-                        " target to %#x.\n",
-                        tid, inst->readPC(), target);
-            } else if (BTB.valid(pred_PC, asid)) {
+                DPRINTF(InOrderBPred, "[tid:%i]: Setting %s predicted"
+                        " target to %s.\n",
+                        tid, inst->pcState(), target);
+            } else if (BTB.valid(predPC.instAddr(), asid)) {
                 ++BTBHits;
 
                 // If it's not a return, use the BTB to get the target addr.
-                target = BTB.lookup(pred_PC, asid);
+                target = BTB.lookup(predPC.instAddr(), asid);
 
-                DPRINTF(InOrderBPred, "[tid:%i]: [asid:%i] Instruction %#x "
-                        "predicted target is %#x.\n",
-                        tid, asid, inst->readPC(), target);
+                DPRINTF(InOrderBPred, "[tid:%i]: [asid:%i] Instruction %s "
+                        "predicted target is %s.\n",
+                        tid, asid, inst->pcState(), target);
             } else {
                 DPRINTF(InOrderBPred, "[tid:%i]: BTB doesn't have a "
                         "valid entry.\n",tid);
@@ -265,14 +264,7 @@ BPredUnit::predict(DynInstPtr &inst, Addr &pred_PC, ThreadID tid)
 
     if (pred_taken) {
         // Set the PC and the instruction's predicted target.
-        pred_PC = target;
-    } else {
-#if ISA_HAS_DELAY_SLOT
-        // This value will be inst->PC + 4 (nextPC)
-        // Delay Slot archs need this to be inst->PC + 8 (nextNPC)
-        // so we increment one more time here.
-        pred_PC = pred_PC + instSize;
-#endif
+        predPC = target;
     }
 
     predHist[tid].push_front(predict_record);
@@ -296,7 +288,7 @@ BPredUnit::update(const InstSeqNum &done_sn, ThreadID tid)
     while (!predHist[tid].empty() &&
            predHist[tid].back().seqNum <= done_sn) {
         // Update the branch predictor with the correct results.
-        BPUpdate(predHist[tid].back().PC,
+        BPUpdate(predHist[tid].back().pc.instAddr(),
                  predHist[tid].back().predTaken,
                  predHist[tid].back().bpHistory);
 
@@ -314,13 +306,13 @@ BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid, ThreadID asid)
            pred_hist.front().seqNum > squashed_sn) {
         if (pred_hist.front().usedRAS) {
             DPRINTF(InOrderBPred, "BranchPred: [tid:%i]: Restoring top of RAS "
-                    "to: %i, target: %#x.\n",
+                    "to: %i, target: %s.\n",
                     tid,
                     pred_hist.front().RASIndex,
-                    pred_hist.front().RASTarget);
+                    pred_hist.front().rasTarget);
 
             RAS[tid].restore(pred_hist.front().RASIndex,
-                             pred_hist.front().RASTarget);
+                             pred_hist.front().rasTarget);
 
         } else if (pred_hist.front().wasCall) {
             DPRINTF(InOrderBPred, "BranchPred: [tid:%i]: Removing speculative "
@@ -340,7 +332,7 @@ BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid, ThreadID asid)
 
 void
 BPredUnit::squash(const InstSeqNum &squashed_sn,
-                  const Addr &corr_target,
+                  const TheISA::PCState &corrTarget,
                   bool actually_taken,
                   ThreadID tid,
                   ThreadID asid)
@@ -354,8 +346,8 @@ BPredUnit::squash(const InstSeqNum &squashed_sn,
     ++condIncorrect;
 
     DPRINTF(InOrderBPred, "[tid:%i]: Squashing from sequence number %i, "
-            "setting target to %#x.\n",
-            tid, squashed_sn, corr_target);
+            "setting target to %s.\n",
+            tid, squashed_sn, corrTarget);
 
     squash(squashed_sn, tid);
 
@@ -380,13 +372,13 @@ BPredUnit::squash(const InstSeqNum &squashed_sn,
             ++RASIncorrect;
         }
 
-        BPUpdate((*hist_it).PC, actually_taken,
+        BPUpdate((*hist_it).pc.instAddr(), actually_taken,
                  pred_hist.front().bpHistory);
 
-        BTB.update((*hist_it).PC, corr_target, asid);
+        BTB.update((*hist_it).pc.instAddr(), corrTarget, asid);
 
         DPRINTF(InOrderBPred, "[tid:%i]: Removing history for [sn:%i] "
-                "PC %#x.\n", tid, (*hist_it).seqNum, (*hist_it).PC);
+                "PC %s.\n", tid, (*hist_it).seqNum, (*hist_it).pc);
 
         pred_hist.erase(hist_it);
 
@@ -424,7 +416,7 @@ BPredUnit::BPSquash(void *bp_history)
 
 
 bool
-BPredUnit::BPLookup(Addr &inst_PC, void * &bp_history)
+BPredUnit::BPLookup(Addr inst_PC, void * &bp_history)
 {
     if (predictor == Local) {
         return localBP->lookup(inst_PC, bp_history);
@@ -437,7 +429,7 @@ BPredUnit::BPLookup(Addr &inst_PC, void * &bp_history)
 
 
 void
-BPredUnit::BPUpdate(Addr &inst_PC, bool taken, void *bp_history)
+BPredUnit::BPUpdate(Addr inst_PC, bool taken, void *bp_history)
 {
     if (predictor == Local) {
         localBP->update(inst_PC, taken, bp_history);
diff --git a/src/cpu/inorder/resources/bpred_unit.hh b/src/cpu/inorder/resources/bpred_unit.hh
index 881bfcc95..3b1c0f4ef 100644
--- a/src/cpu/inorder/resources/bpred_unit.hh
+++ b/src/cpu/inorder/resources/bpred_unit.hh
@@ -83,11 +83,12 @@ class BPredUnit
      * Predicts whether or not the instruction is a taken branch, and the
      * target of the branch if it is taken.
      * @param inst The branch instruction.
-     * @param pred_PC The predicted PC is passed back through this parameter.
+     * @param predPC The predicted PC is passed back through this parameter.
      * @param tid The thread id.
      * @return Returns if the branch is taken or not.
      */
-    bool predict(ThePipeline::DynInstPtr &inst, Addr &pred_PC, ThreadID tid);
+    bool predict(ThePipeline::DynInstPtr &inst,
+            TheISA::PCState &predPC, ThreadID tid);
 
     // @todo: Rename this function.
     void BPUncond(void * &bp_history);
@@ -114,12 +115,13 @@ class BPredUnit
      * corrects that sn's update with the proper address and taken/not taken.
      * @param squashed_sn The sequence number to squash any younger updates up
      * until.
-     * @param corr_target The correct branch target.
+     * @param corrTarget The correct branch target.
      * @param actually_taken The correct branch direction.
      * @param tid The thread id.
      */
-    void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
-                bool actually_taken, ThreadID tid, ThreadID asid = 0);
+    void squash(const InstSeqNum &squashed_sn,
+                const TheISA::PCState &corrTarget, bool actually_taken,
+                ThreadID tid, ThreadID asid = 0);
 
     /**
      * @param bp_history Pointer to the history object.  The predictor
@@ -134,7 +136,7 @@ class BPredUnit
      * has the branch predictor state associated with the lookup.
      * @return Whether the branch is taken or not taken.
      */
-    bool BPLookup(Addr &inst_PC, void * &bp_history);
+    bool BPLookup(Addr instPC, void * &bp_history);
 
     /**
      * Looks up a given PC in the BTB to see if a matching entry exists.
@@ -149,26 +151,26 @@ class BPredUnit
      * @param inst_PC The PC to look up.
      * @return The address of the target of the branch.
      */
-    Addr BTBLookup(Addr &inst_PC)
-    { return BTB.lookup(inst_PC, 0); }
+    TheISA::PCState BTBLookup(Addr instPC)
+    { return BTB.lookup(instPC, 0); }
 
     /**
      * Updates the BP with taken/not taken information.
-     * @param inst_PC The branch's PC that will be updated.
+     * @param instPC The branch's PC that will be updated.
      * @param taken Whether the branch was taken or not taken.
      * @param bp_history Pointer to the branch predictor state that is
      * associated with the branch lookup that is being updated.
      * @todo Make this update flexible enough to handle a global predictor.
      */
-    void BPUpdate(Addr &inst_PC, bool taken, void *bp_history);
+    void BPUpdate(Addr instPC, bool taken, void *bp_history);
 
     /**
      * Updates the BTB with the target of a branch.
      * @param inst_PC The branch's PC that will be updated.
      * @param target_PC The branch's target that will be added to the BTB.
      */
-    void BTBUpdate(Addr &inst_PC, Addr &target_PC)
-    { BTB.update(inst_PC, target_PC,0); }
+    void BTBUpdate(Addr instPC, const TheISA::PCState &targetPC)
+    { BTB.update(instPC, targetPC, 0); }
 
     void dump();
 
@@ -181,22 +183,22 @@ class BPredUnit
          * Makes a predictor history struct that contains any
          * information needed to update the predictor, BTB, and RAS.
          */
-        PredictorHistory(const InstSeqNum &seq_num, const Addr &inst_PC,
-                         bool pred_taken, void *bp_history,
-                         ThreadID _tid)
-            : seqNum(seq_num), PC(inst_PC), RASTarget(0),
-              RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0),
-              wasCall(0), bpHistory(bp_history)
-        { }
+        PredictorHistory(const InstSeqNum &seq_num,
+                         const TheISA::PCState &instPC, bool pred_taken,
+                         void *bp_history, ThreadID _tid)
+            : seqNum(seq_num), pc(instPC), rasTarget(0), RASIndex(0),
+              tid(_tid), predTaken(pred_taken), usedRAS(0), wasCall(0),
+              bpHistory(bp_history)
+        {}
 
         /** The sequence number for the predictor history entry. */
         InstSeqNum seqNum;
 
         /** The PC associated with the sequence number. */
-        Addr PC;
+        TheISA::PCState pc;
 
         /** The RAS target (only valid if a return). */
-        Addr RASTarget;
+        TheISA::PCState rasTarget;
 
         /** The RAS index of the instruction (only valid if a call). */
         unsigned RASIndex;
diff --git a/src/cpu/inorder/resources/branch_predictor.cc b/src/cpu/inorder/resources/branch_predictor.cc
index b971d959a..33b67ce4a 100644
--- a/src/cpu/inorder/resources/branch_predictor.cc
+++ b/src/cpu/inorder/resources/branch_predictor.cc
@@ -84,41 +84,34 @@ BranchPredictor::execute(int slot_num)
                 DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
                         "skipping prediction \n", tid, inst->seqNum);
             } else {
-                Addr pred_PC = inst->readNextPC();
+                TheISA::PCState predPC = inst->pcState();
+                TheISA::advancePC(predPC, inst->staticInst);
 
                 if (inst->isControl()) {
                     // If not, the pred_PC be updated to pc+8
                     // If predicted, the pred_PC will be updated to new target
                     // value
-                    bool predict_taken = branchPred.predict(inst, pred_PC, tid);
+                    bool predict_taken = branchPred.predict(inst, predPC, tid);
 
                     if (predict_taken) {
                         DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch "
                                 "predicted true.\n", tid, seq_num);
-
-                        inst->setPredTarg(pred_PC);
-
                         predictedTaken++;
                     } else {
                         DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch "
                                 "predicted false.\n", tid, seq_num);
-
-                        if (inst->isCondDelaySlot())
-                        {
-                            inst->setPredTarg(inst->readPC() + (2 * instSize));
-                        } else {
-                            inst->setPredTarg(pred_PC);
-                        }
-
                         predictedNotTaken++;
                     }
 
+                    inst->setPredTarg(predPC);
+
                     inst->setBranchPred(predict_taken);
 
                     DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Predicted PC is "
-                            "%08p.\n", tid, seq_num, pred_PC);
+                            "%s.\n", tid, seq_num, predPC);
 
                 } else {
+                    inst->setPredTarg(predPC);
                     //DPRINTF(InOrderBPred, "[tid:%i]: Ignoring [sn:%i] "
                     //      "because this isn't "
                     //      "a control instruction.\n", tid, seq_num);
@@ -166,10 +159,9 @@ BranchPredictor::squash(DynInstPtr inst, int squash_stage,
     squash_seq_num = squash_seq_num - 1;
 #endif
 
-    if(squash_stage>=ThePipeline::BackEndStartStage) {
-        Addr corr_targ=inst->readPredPC();
-        bool taken=inst->predTaken();
-        branchPred.squash(squash_seq_num,corr_targ,taken,tid);
+    if (squash_stage >= ThePipeline::BackEndStartStage) {
+        bool taken = inst->predTaken();
+        branchPred.squash(squash_seq_num, inst->readPredTarg(), taken, tid);
     } else {
         branchPred.squash(squash_seq_num, tid);
     }
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 73deacb12..e7f689ffa 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -392,15 +392,16 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
     unsigned slot_idx = cache_req->getSlot();
 
     if (tlb_mode == TheISA::TLB::Execute) {
-            inst->fetchMemReq = new Request(inst->readTid(), aligned_addr,
-                                            acc_size, flags, inst->readPC(),
-                                            cpu->readCpuId(), inst->readTid());
-            cache_req->memReq = inst->fetchMemReq;
+        inst->fetchMemReq =
+            new Request(inst->readTid(), aligned_addr, acc_size, flags,
+                        inst->instAddr(), cpu->readCpuId(), inst->readTid());
+        cache_req->memReq = inst->fetchMemReq;
     } else {
         if (!cache_req->is2ndSplit()) {            
-            inst->dataMemReq = new Request(cpu->asid[tid], aligned_addr,
-                                           acc_size, flags, inst->readPC(),
-                                           cpu->readCpuId(), inst->readTid());
+            inst->dataMemReq =
+                new Request(cpu->asid[tid], aligned_addr, acc_size, flags,
+                            inst->instAddr(), cpu->readCpuId(),
+                            inst->readTid());
             cache_req->memReq = inst->dataMemReq;
         } else {
             assert(inst->splitInst);
@@ -409,7 +410,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
                                             inst->split2ndAddr,
                                             acc_size, 
                                             flags, 
-                                            inst->readPC(),
+                                            inst->instAddr(),
                                             cpu->readCpuId(), 
                                             tid);
             cache_req->memReq = inst->splitMemReq;            
@@ -754,7 +755,8 @@ CacheUnit::execute(int slot_num)
 
 
             DPRINTF(InOrderCachePort, "[tid:%i]: Instruction [sn:%i] is: %s\n",
-                    tid, seq_num, inst->staticInst->disassemble(inst->PC));
+                    tid, seq_num,
+                    inst->staticInst->disassemble(inst->instAddr()));
 
             removeAddrDependency(inst);
             
@@ -771,7 +773,7 @@ CacheUnit::execute(int slot_num)
                     tid, inst->seqNum);
             DPRINTF(InOrderStall,
                     "STALL: [tid:%i]: Fetch miss from %08p\n",
-                    tid, cache_req->inst->readPC());
+                    tid, cache_req->inst->instAddr());
             cache_req->setCompleted(false);
             //cache_req->setMemStall(true);            
         }
@@ -1046,21 +1048,22 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
             // @todo: update thsi
             ExtMachInst ext_inst;
             StaticInstPtr staticInst = NULL;
-            Addr inst_pc = inst->readPC();
+            TheISA::PCState instPC = inst->pcState();
             MachInst mach_inst = 
                 TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
                              (cache_pkt->getPtr<uint8_t>()));
 
             predecoder.setTC(cpu->thread[tid]->getTC());
-            predecoder.moreBytes(inst_pc, inst_pc, mach_inst);
-            ext_inst = predecoder.getExtMachInst();
+            predecoder.moreBytes(instPC, inst->instAddr(), mach_inst);
+            ext_inst = predecoder.getExtMachInst(instPC);
+            inst->pcState(instPC);
 
             inst->setMachInst(ext_inst);
 
             // Set Up More TraceData info
             if (inst->traceData) {
                 inst->traceData->setStaticInst(inst->staticInst);
-                inst->traceData->setPC(inst->readPC());
+                inst->traceData->setPC(instPC);
             }
 
         } else if (inst->staticInst && inst->isMemRef()) {
@@ -1149,7 +1152,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
     } else {
         DPRINTF(InOrderCachePort,
                 "[tid:%u] Miss on block @ %08p completed, but squashed\n",
-                tid, cache_req->inst->readPC());
+                tid, cache_req->inst->instAddr());
         cache_req->setMemAccCompleted();
     }
 }
diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc
index 91e788fbc..4342042e9 100644
--- a/src/cpu/inorder/resources/execution_unit.cc
+++ b/src/cpu/inorder/resources/execution_unit.cc
@@ -91,8 +91,8 @@ ExecutionUnit::execute(int slot_num)
 
     exec_req->fault = NoFault;
 
-    DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] %s.\n",
-            tid, seq_num, inst->readPC(), inst->instName());
+    DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
+            tid, seq_num, inst->pcState(), inst->instName());
 
     switch (exec_req->cmd)
     {
@@ -124,58 +124,61 @@ ExecutionUnit::execute(int slot_num)
                         if (inst->isDirectCtrl()) {
                             assert(!inst->isIndirectCtrl());
 
+                            TheISA::PCState pc = inst->pcState();
+                            TheISA::advancePC(pc, inst->staticInst);
+                            inst->setPredTarg(pc);
+
                             if (inst->predTaken() && inst->isCondDelaySlot()) {
                                 inst->bdelaySeqNum = seq_num;
-                                inst->setPredTarg(inst->nextPC);
 
                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
-                                        " branch inst [sn:%i] PC %#x mis"
+                                        " branch inst [sn:%i] PC %s mis"
                                         "predicted as taken.\n", tid,
-                                        seq_num, inst->PC);
+                                        seq_num, inst->pcState());
                             } else if (!inst->predTaken() &&
                                        inst->isCondDelaySlot()) {
                                 inst->bdelaySeqNum = seq_num;
-                                inst->setPredTarg(inst->nextPC);
                                 inst->procDelaySlotOnMispred = true;
 
                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
-                                        " branch inst [sn:%i] PC %#x mis"
+                                        " branch inst [sn:%i] PC %s mis"
                                         "predicted as not taken.\n", tid,
-                                        seq_num, inst->PC);
+                                        seq_num, inst->pcState());
                             } else {
 #if ISA_HAS_DELAY_SLOT
                                 inst->bdelaySeqNum = seq_num + 1;
-                                inst->setPredTarg(inst->nextNPC);
 #else
                                 inst->bdelaySeqNum = seq_num;
-                                inst->setPredTarg(inst->nextPC);
 #endif
                                 DPRINTF(InOrderExecute, "[tid:%i]: "
                                         "Misprediction detected at "
-                                        "[sn:%i] PC %#x,\n\t squashing after "
+                                        "[sn:%i] PC %s,\n\t squashing after "
                                         "delay slot instruction [sn:%i].\n",
-                                        tid, seq_num, inst->PC,
+                                        tid, seq_num, inst->pcState(),
                                         inst->bdelaySeqNum);
                                 DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
-                                        " misprediction at %#x\n",
-                                        tid, inst->PC);
+                                        " misprediction at %s\n",
+                                        tid, inst->pcState());
                             }
 
                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting "
-                                    "fetch to %#x.\n", tid,
+                                    "fetch to %s.\n", tid,
                                     inst->readPredTarg());
 
-                        } else if(inst->isIndirectCtrl()){
+                        } else if (inst->isIndirectCtrl()){
+                            TheISA::PCState pc = inst->pcState();
+                            TheISA::advancePC(pc, inst->staticInst);
+                            inst->seqNum = seq_num;
+                            inst->setPredTarg(pc);
+
 #if ISA_HAS_DELAY_SLOT
-                            inst->setPredTarg(inst->nextNPC);
                             inst->bdelaySeqNum = seq_num + 1;
 #else
-                            inst->setPredTarg(inst->nextPC);
                             inst->bdelaySeqNum = seq_num;
 #endif
 
                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting"
-                                    " fetch to %#x.\n", tid,
+                                    " fetch to %s.\n", tid,
                                     inst->readPredTarg());
                         } else {
                             panic("Non-control instruction (%s) mispredict"
@@ -197,14 +200,20 @@ ExecutionUnit::execute(int slot_num)
 
                         if (inst->predTaken()) {
                             predictedTakenIncorrect++;
-                            DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ... PC%#x ... Mispredicts! (Taken)\n",
-                                    tid, inst->seqNum, inst->staticInst->disassemble(inst->PC),
-                                    inst->readPC());
+                            DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
+                                    "PC %s ... Mispredicts! (Taken)\n",
+                                    tid, inst->seqNum,
+                                    inst->staticInst->disassemble(
+                                        inst->instAddr()),
+                                    inst->pcState());
                         } else {
                             predictedNotTakenIncorrect++;
-                            DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ... PC%#x ... Mispredicts! (Not Taken)\n",
-                                    tid, inst->seqNum, inst->staticInst->disassemble(inst->PC),
-                                    inst->readPC());
+                            DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
+                                    "PC %s ... Mispredicts! (Not Taken)\n",
+                                    tid, inst->seqNum,
+                                    inst->staticInst->disassemble(
+                                        inst->instAddr()),
+                                    inst->pcState());
                         }
                         predictedIncorrect++;
                     } else {
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc
index 8a1ec3ce5..3bfe912e7 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc
@@ -44,9 +44,6 @@ FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
       instSize(sizeof(MachInst))
 {
     for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
-        delaySlotInfo[tid].numInsts = 0;
-        delaySlotInfo[tid].targetReady = false;
-
         pcValid[tid] = false;
         pcBlockStage[tid] = 0;
 
@@ -86,53 +83,17 @@ FetchSeqUnit::execute(int slot_num)
       case AssignNextPC:
         {
             if (pcValid[tid]) {
+                inst->pcState(pc[tid]);
+                inst->setMemAddr(pc[tid].instAddr());
 
-                if (delaySlotInfo[tid].targetReady &&
-                    delaySlotInfo[tid].numInsts == 0) {
-                    // Set PC to target
-                    PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
-                    nextPC[tid] = PC[tid] + instSize;        //next_NPC
-                    nextNPC[tid] = PC[tid] + (2 * instSize);
-
-                    delaySlotInfo[tid].targetReady = false;
-
-                    DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to delay "
-                            "slot target\n",tid);
-                }
+                pc[tid].advance(); //XXX HACK!
+                inst->setPredTarg(pc[tid]);
 
-                inst->setPC(PC[tid]);
-                inst->setNextPC(PC[tid] + instSize);
-                inst->setNextNPC(PC[tid] + (instSize * 2));
-
-#if ISA_HAS_DELAY_SLOT
-                inst->setPredTarg(inst->readNextNPC());
-#else
-                inst->setPredTarg(inst->readNextPC());
-#endif
-                inst->setMemAddr(PC[tid]);
                 inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
 
                 DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to "
-                        "PC %08p, NPC %08p, NNPC %08p\n", tid,
-                        inst->seqNum, inst->readPC(), inst->readNextPC(),
-                        inst->readNextNPC());
-
-                if (delaySlotInfo[tid].numInsts > 0) {
-                    --delaySlotInfo[tid].numInsts;
-
-                    // It's OK to set PC to target of branch
-                    if (delaySlotInfo[tid].numInsts == 0) {
-                        delaySlotInfo[tid].targetReady = true;
-                    }
-
-                    DPRINTF(InOrderFetchSeq, "[tid:%i]: %i delay slot inst(s) "
-                            "left to process.\n", tid,
-                            delaySlotInfo[tid].numInsts);
-                }
-
-                PC[tid] = nextPC[tid];
-                nextPC[tid] = nextNPC[tid];
-                nextNPC[tid] += instSize;
+                        "PC %s\n", tid, inst->seqNum,
+                        inst->pcState());
 
                 fs_req->done();
             } else {
@@ -147,18 +108,21 @@ FetchSeqUnit::execute(int slot_num)
             if (inst->isControl()) {
                 // If it's a return, then we must wait for resolved address.
                 if (inst->isReturn() && !inst->predTaken()) {
-                    cpu->pipelineStage[stage_num]->toPrevStages->stageBlock[stage_num][tid] = true;
+                    cpu->pipelineStage[stage_num]->
+                        toPrevStages->stageBlock[stage_num][tid] = true;
                     pcValid[tid] = false;
                     pcBlockStage[tid] = stage_num;
                 } else if (inst->isCondDelaySlot() && !inst->predTaken()) {
                 // Not-Taken AND Conditional Control
-                    DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%08p] "
-                            "Predicted Not-Taken Cond. "
-                            "Delay inst. Skipping delay slot and  Updating PC to %08p\n",
-                            tid, inst->seqNum, inst->readPC(), inst->readPredTarg());
+                    DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%s] "
+                            "Predicted Not-Taken Cond. Delay inst. Skipping "
+                            "delay slot and  Updating PC to %s\n",
+                            tid, inst->seqNum, inst->pcState(),
+                            inst->readPredTarg());
 
-                    DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
-                            tid, stage_num, seq_num);
+                    DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
+                            "start from stage %i, after [sn:%i].\n", tid,
+                            stage_num, seq_num);
 
                     inst->bdelaySeqNum = seq_num;
                     inst->squashingStage = stage_num;
@@ -168,33 +132,26 @@ FetchSeqUnit::execute(int slot_num)
                     // Not-Taken Control
                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted "
                             "Not-Taken Control "
-                            "inst. updating PC to %08p\n", tid, inst->seqNum,
-                            inst->readNextPC());
+                            "inst. updating PC to %s\n", tid, inst->seqNum,
+                            inst->readPredTarg());
 #if ISA_HAS_DELAY_SLOT
-                    ++delaySlotInfo[tid].numInsts;
-                    delaySlotInfo[tid].targetReady = false;
-                    delaySlotInfo[tid].targetAddr = inst->readNextNPC();
-#else
-                    assert(delaySlotInfo[tid].numInsts == 0);
+                    pc[tid] = inst->pcState();
+                    advancePC(pc[tid], inst->staticInst);
 #endif
                 } else if (inst->predTaken()) {
                     // Taken Control
 #if ISA_HAS_DELAY_SLOT
-                    ++delaySlotInfo[tid].numInsts;
-                    delaySlotInfo[tid].targetReady = false;
-                    delaySlotInfo[tid].targetAddr = inst->readPredTarg();
+                    pc[tid] = inst->readPredTarg();
 
                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay"
-                            " slot target to PC %08p\n", tid, inst->seqNum,
+                            " slot target to PC %s\n", tid, inst->seqNum,
                             inst->readPredTarg());
                     inst->bdelaySeqNum = seq_num + 1;
 #else
                     inst->bdelaySeqNum = seq_num;
-                    assert(delaySlotInfo[tid].numInsts == 0);
 #endif
 
                     inst->squashingStage = stage_num;
-
                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
                             "start from stage %i, after [sn:%i].\n",
                             tid, stage_num, inst->bdelaySeqNum);
@@ -225,11 +182,12 @@ FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
 
     // Squash inside current resource, so if there needs to be fetching on
     // same cycle the fetch information will be correct.
-    // squash(inst, stage_num, inst->bdelaySeqNum, tid);
 
     // Schedule Squash Through-out Resource Pool
-    cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
+    cpu->resPool->scheduleEvent(
+            (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
 }
+
 void
 FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
                      InstSeqNum squash_seq_num, ThreadID tid)
@@ -241,8 +199,15 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
 
     // Handles the case where we are squashing because of something that is
     // not a branch...like a memory stall
-    Addr new_PC = (inst->isControl()) ?
-        inst->readPredTarg() : inst->readPC() + instSize;
+    TheISA::PCState newPC;
+    if (inst->isControl()) {
+        newPC = inst->readPredTarg();
+    } else {
+        TheISA::PCState thisPC = inst->pcState();
+        assert(inst->staticInst);
+        advancePC(thisPC, inst->staticInst);
+        newPC = thisPC;
+    }
 
     if (squashSeqNum[tid] <= done_seq_num &&
         lastSquashCycle[tid] == curTick) {
@@ -258,31 +223,25 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
         // the last done_seq_num then this is the delay slot inst.
         if (cpu->nextInstSeqNum(tid) != done_seq_num &&
             !inst->procDelaySlotOnMispred) {
-            delaySlotInfo[tid].numInsts = 0;
-            delaySlotInfo[tid].targetReady = false;
 
             // Reset PC
-            PC[tid] = new_PC;
-            nextPC[tid] = new_PC + instSize;
-            nextNPC[tid] = new_PC + (2 * instSize);
+            pc[tid] = newPC;
+#if ISA_HAS_DELAY_SLOT
+            TheISA::advancePC(pc[tid], inst->staticInst);
+#endif
 
-            DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %08p.\n",
-                    tid, PC[tid]);
+            DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
+                    tid, newPC);
         } else {
-#if !ISA_HAS_DELAY_SLOT
-            assert(0);
-#endif
+            assert(ISA_HAS_DELAY_SLOT);
 
-            delaySlotInfo[tid].numInsts = 1;
-            delaySlotInfo[tid].targetReady = false;
-            delaySlotInfo[tid].targetAddr = (inst->procDelaySlotOnMispred) ?
-                inst->branchTarget() : new_PC;
+            pc[tid] = (inst->procDelaySlotOnMispred) ?
+                inst->branchTarget() : newPC;
 
             // Reset PC to Delay Slot Instruction
             if (inst->procDelaySlotOnMispred) {
-                PC[tid] = new_PC;
-                nextPC[tid] = new_PC + instSize;
-                nextNPC[tid] = new_PC + (2 * instSize);
+                // Reset PC
+                pc[tid] = newPC;
             }
 
         }
@@ -309,18 +268,13 @@ FetchSeqUnit::FetchSeqEvent::process()
     FetchSeqUnit* fs_res = dynamic_cast<FetchSeqUnit*>(resource);
     assert(fs_res);
 
-    for (int i=0; i < MaxThreads; i++) {
-        fs_res->PC[i] = fs_res->cpu->readPC(i);
-        fs_res->nextPC[i] = fs_res->cpu->readNextPC(i);
-        fs_res->nextNPC[i] = fs_res->cpu->readNextNPC(i);
-        DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC:%08p NPC:%08p "
-                "NNPC:%08p.\n", fs_res->PC[i], fs_res->nextPC[i],
-                fs_res->nextNPC[i]);
+    for (int i = 0; i < MaxThreads; i++) {
+        fs_res->pc[i] = fs_res->cpu->pcState(i);
+        DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC: %s.\n",
+                fs_res->pc[i]);
 
         fs_res->pcValid[i] = true;
     }
-
-    //cpu->fetchPriorityList.push_back(tid);
 }
 
 
@@ -329,22 +283,17 @@ FetchSeqUnit::activateThread(ThreadID tid)
 {
     pcValid[tid] = true;
 
-    PC[tid] = cpu->readPC(tid);
-    nextPC[tid] = cpu->readNextPC(tid);
-    nextNPC[tid] = cpu->readNextNPC(tid);
+    pc[tid] = cpu->pcState(tid);
 
     cpu->fetchPriorityList.push_back(tid);
 
-    DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC:%08p NPC:%08p "
-            "NNPC:%08p.\n", tid, PC[tid], nextPC[tid], nextNPC[tid]);
+    DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC: %s.\n",
+            tid, pc[tid]);
 }
 
 void
 FetchSeqUnit::deactivateThread(ThreadID tid)
 {
-    delaySlotInfo[tid].numInsts = 0;
-    delaySlotInfo[tid].targetReady = false;
-
     pcValid[tid] = false;
     pcBlockStage[tid] = 0;
 
@@ -375,18 +324,14 @@ FetchSeqUnit::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
          *  switch was right after the branch. Thus, if it's not, then
          *  we are updating incorrectly here
          */
-        assert(cpu->thread[tid]->lastBranchNextPC == inst->readPC());
-        
-        PC[tid] = cpu->thread[tid]->lastBranchNextNPC;
-        nextPC[tid] = PC[tid] + instSize;
-        nextNPC[tid] = nextPC[tid] + instSize;
+        assert(cpu->nextInstAddr(tid) == inst->instAddr());
+        pc[tid] = cpu->thread[tid]->lastBranchPC;
     } else {
-        PC[tid] = inst->readNextPC();
-        nextPC[tid] = inst->readNextNPC();
-        nextNPC[tid] = inst->readNextNPC() + instSize;        
+        pc[tid] = inst->pcState();
     }
+    assert(inst->staticInst);
+    advancePC(pc[tid], inst->staticInst);
     
     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating PCs due to Context Switch."
-            "Assigning  PC:%08p NPC:%08p NNPC:%08p.\n", tid, PC[tid], 
-            nextPC[tid], nextNPC[tid]);
+            "Assigning  PC: %s.\n", tid, pc[tid]);
 }
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.hh b/src/cpu/inorder/resources/fetch_seq_unit.hh
index aab462224..a258dc0e5 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.hh
+++ b/src/cpu/inorder/resources/fetch_seq_unit.hh
@@ -80,22 +80,7 @@ class FetchSeqUnit : public Resource {
     bool pcValid[ThePipeline::MaxThreads];
     int pcBlockStage[ThePipeline::MaxThreads];
 
-    TheISA::IntReg PC[ThePipeline::MaxThreads];
-    TheISA::IntReg nextPC[ThePipeline::MaxThreads];
-    TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
-
-    /** Tracks delay slot information for threads in ISAs which use
-     *	delay slots;
-     */
-    struct DelaySlotInfo {
-        InstSeqNum delaySlotSeqNum;
-        InstSeqNum branchSeqNum;
-        int numInsts;
-        Addr targetAddr;
-        bool targetReady;
-    };
-
-    DelaySlotInfo delaySlotInfo[ThePipeline::MaxThreads];
+    TheISA::PCState pc[ThePipeline::MaxThreads];
 
     /** Squash Seq. Nums*/
     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh
index 5c62c7751..eb1bf55f0 100644
--- a/src/cpu/inorder/resources/tlb_unit.hh
+++ b/src/cpu/inorder/resources/tlb_unit.hh
@@ -111,8 +111,10 @@ class TLBUnitRequest : public ResourceRequest {
             aligned_addr = inst->getMemAddr();
             req_size = sizeof(TheISA::MachInst);
             flags = 0;
-            inst->fetchMemReq = new Request(inst->readTid(), aligned_addr, req_size,
-                                            flags, inst->readPC(), res->cpu->readCpuId(), inst->readTid());
+            inst->fetchMemReq = new Request(inst->readTid(), aligned_addr,
+                                            req_size, flags, inst->instAddr(),
+                                            res->cpu->readCpuId(),
+                                            inst->readTid());
             memReq = inst->fetchMemReq;
         } else {
             aligned_addr = inst->getMemAddr();;
@@ -123,8 +125,10 @@ class TLBUnitRequest : public ResourceRequest {
                 req_size = 8;
             }
 
-            inst->dataMemReq = new Request(inst->readTid(), aligned_addr, req_size,
-                                   flags, inst->readPC(), res->cpu->readCpuId(), inst->readTid());
+            inst->dataMemReq = new Request(inst->readTid(), aligned_addr,
+                                           req_size, flags, inst->instAddr(),
+                                           res->cpu->readCpuId(),
+                                           inst->readTid());
             memReq = inst->dataMemReq;
         }
     }