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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-08 22:21:27 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-08 22:21:27 -0700 |
| commit | 7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 (patch) | |
| tree | 4c212f665de2628eac6f84d389de7a79b6d0b933 /src/cpu/inorder/resources | |
| parent | 08043c777f1f05f5e14581950013461f328965be (diff) | |
| download | gem5-7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60.tar.xz | |
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
Diffstat (limited to 'src/cpu/inorder/resources')
| -rw-r--r-- | src/cpu/inorder/resources/tlb_unit.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc index 8f8ba144e..b3757d707 100644 --- a/src/cpu/inorder/resources/tlb_unit.cc +++ b/src/cpu/inorder/resources/tlb_unit.cc @@ -99,7 +99,7 @@ TLBUnit::execute(int slot_idx) { tlb_req->fault = this->cpu->itb->translateAtomic(tlb_req->memReq, - cpu->thread[tid]->getTC()); + cpu->thread[tid]->getTC(), false, true); if (tlb_req->fault != NoFault) { DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating " |