inorder: no dep. tracking for zero reg

this causes forwarding a bad value register value

3 files changed, 23 insertions, 5 deletions

diff --git a/src/cpu/inorder/resources/decode_unit.cc b/src/cpu/inorder/resources/decode_unit.cc
index 0ab9d96c7..1ba5c204a 100644
--- a/src/cpu/inorder/resources/decode_unit.cc
+++ b/src/cpu/inorder/resources/decode_unit.cc
@@ -62,6 +62,10 @@ DecodeUnit::execute(int slot_num)
         {
             assert(!inst->staticInst->isMacroop());
 
+            DPRINTF(Decode,"Decoded instruction [sn:%i]: %s : 0x%x\n",
+                    inst->seqNum, inst->instName(),
+                    inst->staticInst->machInst);
+
             inst->setBackSked(cpu->createBackEndSked(inst));
 
             if (inst->backSked != NULL) {
diff --git a/src/cpu/inorder/resources/graduation_unit.cc b/src/cpu/inorder/resources/graduation_unit.cc
index 9c17db945..641d7b5ad 100644
--- a/src/cpu/inorder/resources/graduation_unit.cc
+++ b/src/cpu/inorder/resources/graduation_unit.cc
@@ -78,8 +78,8 @@ GraduationUnit::execute(int slot_num)
             }
 
             DPRINTF(InOrderGraduation,
-                    "[tid:%i] Graduating instruction %s [sn:%i].\n",
-                    tid, inst->instName(), inst->seqNum);
+                    "[tid:%i]:[sn:%i]: Graduating instruction %s.\n",
+                    tid, inst->seqNum, inst->instName());
 
             // Release Non-Speculative "Block" on instructions that could not
             // execute because there was a non-speculative inst. active.
diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc
index 392239d42..1adee09db 100644
--- a/src/cpu/inorder/resources/use_def.cc
+++ b/src/cpu/inorder/resources/use_def.cc
@@ -181,9 +181,16 @@ UseDefUnit::execute(int slot_idx)
             RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
             inst->flattenSrcReg(ud_idx, flat_idx);
             
-            DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Attempting to read source "
-                    "register idx %i (reg #%i, flat#%i).\n",
-                    tid, seq_num, ud_idx, reg_idx, flat_idx);
+            if (flat_idx == TheISA::ZeroReg) {
+                DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Ignoring Reading of ISA-ZeroReg "
+                        "(Int. Reg %i).\n", tid, inst->seqNum, flat_idx);
+                ud_req->done();
+                return;
+            } else {
+                DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Attempting to read source "
+                        "register idx %i (reg #%i, flat#%i).\n",
+                        tid, seq_num, ud_idx, reg_idx, flat_idx);
+            }
 
             if (regDepMap[tid]->canRead(reg_type, flat_idx, inst)) {
                 switch (reg_type)
@@ -324,6 +331,13 @@ UseDefUnit::execute(int slot_idx)
             RegIndex reg_idx = inst->_destRegIdx[ud_idx];
             RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
 
+            if (flat_idx == TheISA::ZeroReg) {
+                DPRINTF(IntRegs, "[tid:%i]: Ignoring Writing of ISA-ZeroReg "
+                        "(Int. Reg %i)\n", tid, flat_idx);
+                ud_req->done();
+                return;
+            }
+
             if (regDepMap[tid]->canWrite(reg_type, flat_idx, inst)) {
                 DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Flattening register idx %i "
                         "(%i) and Attempting to write to Register File.\n",